Skip to content

Commit

Permalink
[AMDGPU] Remove VT helpers isFloatType, isPackedType, simplify isIntT…
Browse files Browse the repository at this point in the history 
…ype (#77987)
  • Loading branch information
@rampitec
rampitec committed Jan 16, 2024
1 parent c4c53ae commit 8e9e4f8
Show file tree
Hide file tree
Showing 7 changed files with 43 additions and 107 deletions.
10 changes: 4 additions & 6 deletions llvm/lib/Target/AMDGPU/BUFInstructions.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -780,9 +780,8 @@ class MUBUF_AtomicRet_Pseudo<string opName, int addrKind,

multiclass MUBUF_Pseudo_Atomics_NO_RTN <string opName,
RegisterClass vdataClass,
ValueType vdataType,
bit isFP = isFloatType<vdataType>.ret> {
let FPAtomic = isFP in {
ValueType vdataType> {
let FPAtomic = vdataType.isFP in {
def _OFFSET : MUBUF_AtomicNoRet_Pseudo <opName, BUFAddrKind.Offset, vdataClass, 0>,
MUBUFAddr64Table <0, NAME>;
def _ADDR64 : MUBUF_AtomicNoRet_Pseudo <opName, BUFAddrKind.Addr64, vdataClass, 0>,
Expand All @@ -804,9 +803,8 @@ multiclass MUBUF_Pseudo_Atomics_NO_RTN <string opName,
multiclass MUBUF_Pseudo_Atomics_RTN <string opName,
RegisterClass vdataClass,
ValueType vdataType,
SDPatternOperator atomic,
bit isFP = isFloatType<vdataType>.ret> {
let FPAtomic = isFP in {
SDPatternOperator atomic> {
let FPAtomic = vdataType.isFP in {
def _OFFSET_RTN : MUBUF_AtomicRet_Pseudo <opName, BUFAddrKind.Offset, vdataClass, 0,
[(set vdataType:$vdata,
(atomic (MUBUFOffset v4i32:$srsrc, i32:$soffset, i32:$offset),
Expand Down
21 changes: 8 additions & 13 deletions llvm/lib/Target/AMDGPU/FLATInstructions.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -535,7 +535,6 @@ multiclass FLAT_Atomic_Pseudo_NO_RTN<
ValueType vt,
ValueType data_vt = vt,
RegisterClass data_rc = vdst_rc,
bit isFP = isFloatType<data_vt>.ret,
RegisterOperand data_op = getLdStRegisterOperand<data_rc>.ret> {
def "" : FLAT_AtomicNoRet_Pseudo <opName,
(outs),
Expand All @@ -544,7 +543,7 @@ multiclass FLAT_Atomic_Pseudo_NO_RTN<
GlobalSaddrTable<0, opName>,
AtomicNoRet <opName, 0> {
let PseudoInstr = NAME;
let FPAtomic = isFP;
let FPAtomic = data_vt.isFP;
let AddedComplexity = -1; // Prefer global atomics if available
}
}
Expand All @@ -555,15 +554,14 @@ multiclass FLAT_Atomic_Pseudo_RTN<
ValueType vt,
ValueType data_vt = vt,
RegisterClass data_rc = vdst_rc,
bit isFP = isFloatType<data_vt>.ret,
RegisterOperand data_op = getLdStRegisterOperand<data_rc>.ret> {
def _RTN : FLAT_AtomicRet_Pseudo <opName,
(outs getLdStRegisterOperand<vdst_rc>.ret:$vdst),
(ins VReg_64:$vaddr, data_op:$vdata, flat_offset:$offset, CPol_GLC1:$cpol),
" $vdst, $vaddr, $vdata$offset$cpol">,
GlobalSaddrTable<0, opName#"_rtn">,
AtomicNoRet <opName, 1> {
let FPAtomic = isFP;
let FPAtomic = data_vt.isFP;
let AddedComplexity = -1; // Prefer global atomics if available
}
}
Expand All @@ -574,10 +572,9 @@ multiclass FLAT_Atomic_Pseudo<
ValueType vt,
ValueType data_vt = vt,
RegisterClass data_rc = vdst_rc,
bit isFP = isFloatType<data_vt>.ret,
RegisterOperand data_op = getLdStRegisterOperand<data_rc>.ret> {
defm "" : FLAT_Atomic_Pseudo_NO_RTN<opName, vdst_rc, vt, data_vt, data_rc, isFP, data_op>;
defm "" : FLAT_Atomic_Pseudo_RTN<opName, vdst_rc, vt, data_vt, data_rc, isFP, data_op>;
defm "" : FLAT_Atomic_Pseudo_NO_RTN<opName, vdst_rc, vt, data_vt, data_rc, data_op>;
defm "" : FLAT_Atomic_Pseudo_RTN<opName, vdst_rc, vt, data_vt, data_rc, data_op>;
}

multiclass FLAT_Global_Atomic_Pseudo_NO_RTN<
Expand All @@ -586,7 +583,6 @@ multiclass FLAT_Global_Atomic_Pseudo_NO_RTN<
ValueType vt,
ValueType data_vt = vt,
RegisterClass data_rc = vdst_rc,
bit isFP = isFloatType<data_vt>.ret,
RegisterOperand data_op = getLdStRegisterOperand<data_rc>.ret> {

def "" : FLAT_AtomicNoRet_Pseudo <opName,
Expand All @@ -597,7 +593,7 @@ multiclass FLAT_Global_Atomic_Pseudo_NO_RTN<
AtomicNoRet <opName, 0> {
let has_saddr = 1;
let PseudoInstr = NAME;
let FPAtomic = isFP;
let FPAtomic = data_vt.isFP;
}

def _SADDR : FLAT_AtomicNoRet_Pseudo <opName,
Expand All @@ -609,7 +605,7 @@ multiclass FLAT_Global_Atomic_Pseudo_NO_RTN<
let has_saddr = 1;
let enabled_saddr = 1;
let PseudoInstr = NAME#"_SADDR";
let FPAtomic = isFP;
let FPAtomic = data_vt.isFP;
}
}

Expand All @@ -619,7 +615,6 @@ multiclass FLAT_Global_Atomic_Pseudo_RTN<
ValueType vt,
ValueType data_vt = vt,
RegisterClass data_rc = vdst_rc,
bit isFP = isFloatType<data_vt>.ret,
RegisterOperand data_op = getLdStRegisterOperand<data_rc>.ret,
RegisterOperand vdst_op = getLdStRegisterOperand<vdst_rc>.ret> {

Expand All @@ -630,7 +625,7 @@ multiclass FLAT_Global_Atomic_Pseudo_RTN<
GlobalSaddrTable<0, opName#"_rtn">,
AtomicNoRet <opName, 1> {
let has_saddr = 1;
let FPAtomic = isFP;
let FPAtomic = data_vt.isFP;
}

def _SADDR_RTN : FLAT_AtomicRet_Pseudo <opName,
Expand All @@ -642,7 +637,7 @@ multiclass FLAT_Global_Atomic_Pseudo_RTN<
let has_saddr = 1;
let enabled_saddr = 1;
let PseudoInstr = NAME#"_SADDR_RTN";
let FPAtomic = isFP;
let FPAtomic = data_vt.isFP;
}
}

Expand Down
103 changes: 23 additions & 80 deletions llvm/lib/Target/AMDGPU/SIInstrInfo.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -281,56 +281,10 @@ def SIfptrunc_round_downward : SDNode<"AMDGPUISD::FPTRUNC_ROUND_DOWNWARD",
// ValueType helpers
//===----------------------------------------------------------------------===//

// Returns 1 if the source arguments have modifiers, 0 if they do not.
class isFloatType<ValueType SrcVT> {
bit ret = !or(!eq(SrcVT.Value, f16.Value),
!eq(SrcVT.Value, bf16.Value),
!eq(SrcVT.Value, f32.Value),
!eq(SrcVT.Value, f64.Value),
!eq(SrcVT.Value, v2f16.Value),
!eq(SrcVT.Value, v2bf16.Value),
!eq(SrcVT.Value, v4f16.Value),
!eq(SrcVT.Value, v4bf16.Value),
!eq(SrcVT.Value, v8f16.Value),
!eq(SrcVT.Value, v8bf16.Value),
!eq(SrcVT.Value, v16f16.Value),
!eq(SrcVT.Value, v16bf16.Value),
!eq(SrcVT.Value, v2f32.Value),
!eq(SrcVT.Value, v4f32.Value),
!eq(SrcVT.Value, v8f32.Value),
!eq(SrcVT.Value, v2f64.Value),
!eq(SrcVT.Value, v4f64.Value));
}

// XXX - do v2i16 instructions?
class isIntType<ValueType SrcVT> {
bit ret = !or(!eq(SrcVT.Value, i8.Value),
!eq(SrcVT.Value, i16.Value),
!eq(SrcVT.Value, i32.Value),
!eq(SrcVT.Value, i64.Value),
!eq(SrcVT.Value, v4i16.Value),
!eq(SrcVT.Value, v8i16.Value),
!eq(SrcVT.Value, v16i16.Value),
!eq(SrcVT.Value, v2i32.Value),
!eq(SrcVT.Value, v4i32.Value),
!eq(SrcVT.Value, v8i32.Value));
bit ret = !and(SrcVT.isInteger, !ne(SrcVT.Value, i1.Value));
}

class isPackedType<ValueType SrcVT> {
bit ret = !or(!eq(SrcVT.Value, v2i16.Value),
!eq(SrcVT.Value, v2f16.Value),
!eq(SrcVT.Value, v2bf16.Value),
!eq(SrcVT.Value, v4f16.Value),
!eq(SrcVT.Value, v4bf16.Value),
!eq(SrcVT.Value, v2i32.Value),
!eq(SrcVT.Value, v2f32.Value),
!eq(SrcVT.Value, v4i32.Value),
!eq(SrcVT.Value, v4f32.Value),
!eq(SrcVT.Value, v8i32.Value),
!eq(SrcVT.Value, v8f32.Value));
}


//===----------------------------------------------------------------------===//
// PatFrags for global memory operations
//===----------------------------------------------------------------------===//
Expand Down Expand Up @@ -1003,7 +957,7 @@ def ExpSrc3 : RegisterOperand<VGPR_32> {

class SDWASrc<ValueType vt> : RegisterOperand<VS_32> {
let OperandNamespace = "AMDGPU";
string Type = !if(isFloatType<vt>.ret, "FP", "INT");
string Type = !if(vt.isFP, "FP", "INT");
let OperandType = "OPERAND_REG_INLINE_C_"#Type#vt.Size;
let DecoderMethod = "decodeSDWASrc"#vt.Size;
let EncoderMethod = "getSDWASrcEncoding";
Expand Down Expand Up @@ -1499,10 +1453,8 @@ class getSDWADstForVT<ValueType VT> {
// Returns the register class to use for source 0 of VOP[12C]
// instructions for the given VT.
class getVOPSrc0ForVT<ValueType VT, bit IsTrue16, bit IsFake16 = 1> {
bit isFP = isFloatType<VT>.ret;

RegisterOperand ret =
!if(isFP,
!if(VT.isFP,
!if(!eq(VT.Size, 64),
VSrc_f64,
!if(!or(!eq(VT.Value, f16.Value), !eq(VT.Value, bf16.Value)),
Expand Down Expand Up @@ -1562,21 +1514,19 @@ class getVregSrcForVT_t16<ValueType VT, bit IsFake16 = 1> {
}

class getSDWASrcForVT <ValueType VT> {
bit isFP = isFloatType<VT>.ret;
RegisterOperand retFlt = !if(!eq(VT.Size, 16), SDWASrc_f16, SDWASrc_f32);
RegisterOperand retInt = !if(!eq(VT.Size, 16), SDWASrc_i16, SDWASrc_i32);
RegisterOperand ret = !if(isFP, retFlt, retInt);
RegisterOperand ret = !if(VT.isFP, retFlt, retInt);
}

// Returns the register class to use for sources of VOP3 instructions for the
// given VT.
class getVOP3SrcForVT<ValueType VT, bit IsTrue16 = 0> {
bit isFP = isFloatType<VT>.ret;
RegisterOperand ret =
!if(!eq(VT.Size, 128),
VRegSrc_128,
!if(!eq(VT.Size, 64),
!if(isFP,
!if(VT.isFP,
!if(!eq(VT.Value, v2f32.Value),
VSrc_v2f32,
VSrc_f64),
Expand All @@ -1585,7 +1535,7 @@ class getVOP3SrcForVT<ValueType VT, bit IsTrue16 = 0> {
VSrc_b64)),
!if(!eq(VT.Value, i1.Value),
SSrc_i1,
!if(isFP,
!if(VT.isFP,
!if(!or(!eq(VT.Value, f16.Value), !eq(VT.Value, bf16.Value)),
!if(IsTrue16, VSrcT_f16, VSrc_f16),
!if(!or(!eq(VT.Value, v2f16.Value), !eq(VT.Value, v2bf16.Value)),
Expand All @@ -1611,10 +1561,9 @@ class getVOP3SrcForVT<ValueType VT, bit IsTrue16 = 0> {

// Src2 of VOP3 DPP instructions cannot be a literal
class getVOP3DPPSrcForVT<ValueType VT> {
bit isFP = isFloatType<VT>.ret;
RegisterOperand ret =
!if (!eq(VT.Value, i1.Value), SSrc_i1,
!if (isFP,
!if (VT.isFP,
!if (!or(!eq(VT.Value, f16.Value), !eq(VT.Value, bf16.Value)), VCSrc_f16,
!if (!or(!eq(VT.Value, v2f16.Value), !eq(VT.Value, v2bf16.Value)), VCSrc_v2f16, VCSrc_f32)),
!if (!eq(VT.Value, i16.Value), VCSrc_b16,
Expand Down Expand Up @@ -1650,14 +1599,12 @@ class isModifierType<ValueType SrcVT> {

// Return type of input modifiers operand for specified input operand
class getSrcMod <ValueType VT, bit IsTrue16 = 0> {
bit isFP = isFloatType<VT>.ret;
bit isPacked = isPackedType<VT>.ret;
Operand ret = !if(!eq(VT.Size, 64),
!if(isFP, FP64InputMods, Int64InputMods),
!if(VT.isFP, FP64InputMods, Int64InputMods),
!if(!eq(VT.Size, 16),
!if(isFP, !if(IsTrue16, FPT16InputMods, FP16InputMods),
!if(IsTrue16, IntT16InputMods, IntOpSelMods)),
!if(isFP, FP32InputMods, Int32InputMods)));
!if(VT.isFP, !if(IsTrue16, FPT16InputMods, FP16InputMods),
!if(IsTrue16, IntT16InputMods, IntOpSelMods)),
!if(VT.isFP, FP32InputMods, Int32InputMods)));
}

class getOpSelMod <ValueType VT> {
Expand All @@ -1667,14 +1614,12 @@ class getOpSelMod <ValueType VT> {

// Return type of input modifiers operand specified input operand for DPP
class getSrcModDPP <ValueType VT> {
bit isFP = isFloatType<VT>.ret;
Operand ret = !if(isFP, FPVRegInputMods, IntVRegInputMods);
Operand ret = !if(VT.isFP, FPVRegInputMods, IntVRegInputMods);
}

class getSrcModDPP_t16 <ValueType VT> {
bit isFP = isFloatType<VT>.ret;
Operand ret =
!if (isFP,
!if (VT.isFP,
!if (!or(!eq(VT.Value, f16.Value), !eq(VT.Value, bf16.Value)),
FPT16VRegInputMods, FPVRegInputMods),
!if (!eq(VT.Value, i16.Value), IntT16VRegInputMods,
Expand All @@ -1683,10 +1628,8 @@ class getSrcModDPP_t16 <ValueType VT> {

// Return type of input modifiers operand for specified input operand for DPP
class getSrcModVOP3DPP <ValueType VT> {
bit isFP = isFloatType<VT>.ret;
bit isPacked = isPackedType<VT>.ret;
Operand ret =
!if (isFP,
!if (VT.isFP,
!if (!or(!eq(VT.Value, f16.Value), !eq(VT.Value, bf16.Value)),
FP16VCSrcInputMods, FP32VCSrcInputMods),
Int32VCSrcInputMods);
Expand Down Expand Up @@ -2330,26 +2273,26 @@ class VOPProfile <list<ValueType> _ArgVT, bit _EnableClamp = 0> {
field bit HasSrc1 = !ne(Src1VT.Value, untyped.Value);
field bit HasSrc2 = !ne(Src2VT.Value, untyped.Value);

field bit HasSrc0FloatMods = isFloatType<Src0VT>.ret;
field bit HasSrc1FloatMods = isFloatType<Src1VT>.ret;
field bit HasSrc2FloatMods = isFloatType<Src2VT>.ret;
field bit HasSrc0FloatMods = Src0VT.isFP;
field bit HasSrc1FloatMods = Src1VT.isFP;
field bit HasSrc2FloatMods = Src2VT.isFP;

field bit HasSrc0IntMods = isIntType<Src0VT>.ret;
field bit HasSrc1IntMods = isIntType<Src1VT>.ret;
field bit HasSrc2IntMods = isIntType<Src2VT>.ret;

field bit HasClamp = !or(isModifierType<Src0VT>.ret, EnableClamp);
field bit HasSDWAClamp = EmitDst;
field bit HasFPClamp = !and(isFloatType<DstVT>.ret, HasClamp);
field bit HasIntClamp = !if(isFloatType<DstVT>.ret, 0, HasClamp);
field bit HasFPClamp = !and(DstVT.isFP, HasClamp);
field bit HasIntClamp = !if(DstVT.isFP, 0, HasClamp);
field bit HasClampLo = HasClamp;
field bit HasClampHi = !and(isPackedType<DstVT>.ret, HasClamp);
field bit HasClampHi = !and(DstVT.isVector, HasClamp);
field bit HasHigh = 0;

field bit IsPacked = isPackedType<Src0VT>.ret;
field bit IsPacked = Src0VT.isVector;
field bit HasOpSel = IsPacked;
field bit HasOMod = !if(IsVOP3P, 0, isFloatType<DstVT>.ret);
field bit HasSDWAOMod = isFloatType<DstVT>.ret;
field bit HasOMod = !if(IsVOP3P, 0, DstVT.isFP);
field bit HasSDWAOMod = DstVT.isFP;

field bit HasModifiers = !or(isModifierType<Src0VT>.ret,
isModifierType<Src1VT>.ret,
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/VOP1Instructions.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -48,7 +48,7 @@ class VOP1_Pseudo <string opName, VOPProfile P, list<dag> pattern=[], bit VOP1On
let mayStore = 0;
let hasSideEffects = 0;

let ReadsModeReg = !or(isFloatType<P.DstVT>.ret, isFloatType<P.Src0VT>.ret);
let ReadsModeReg = !or(P.DstVT.isFP, P.Src0VT.isFP);

let mayRaiseFPException = ReadsModeReg;

Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/VOP2Instructions.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -69,7 +69,7 @@ class VOP2_Pseudo <string opName, VOPProfile P, list<dag> pattern=[], string suf
let mayStore = 0;
let hasSideEffects = 0;

let ReadsModeReg = !or(isFloatType<P.DstVT>.ret, isFloatType<P.Src0VT>.ret);
let ReadsModeReg = !or(P.DstVT.isFP, P.Src0VT.isFP);

let mayRaiseFPException = ReadsModeReg;

Expand Down
6 changes: 3 additions & 3 deletions llvm/lib/Target/AMDGPU/VOPCInstructions.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -108,8 +108,8 @@ class VOPC_NoSdst_Profile<list<SchedReadWrite> sched, ValueType vt0,
let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0,
Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1,
src0_sel:$src0_sel, src1_sel:$src1_sel);
let AsmVOP3Base = !if(isFloatType<Src0VT>.ret, "$src0_modifiers, $src1_modifiers$clamp",
"$src0, $src1");
let AsmVOP3Base = !if(Src0VT.isFP, "$src0_modifiers, $src1_modifiers$clamp",
"$src0, $src1");
let AsmSDWA9 = "$src0_modifiers, $src1_modifiers $src0_sel $src1_sel";
let EmitDst = 0;
}
Expand Down Expand Up @@ -146,7 +146,7 @@ class VOPC_Pseudo <string opName, VOPC_Profile P, list<dag> pattern=[],
let mayStore = 0;
let hasSideEffects = 0;

let ReadsModeReg = isFloatType<P.Src0VT>.ret;
let ReadsModeReg = P.Src0VT.isFP;

let VALU = 1;
let VOPC = 1;
Expand Down
6 changes: 3 additions & 3 deletions llvm/lib/Target/AMDGPU/VOPInstructions.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -152,7 +152,7 @@ class VOP3_Pseudo <string opName, VOPProfile P, list<dag> pattern = [],
let ClampLo = P.HasClampLo;
let ClampHi = P.HasClampHi;

let ReadsModeReg = !or(isFloatType<P.DstVT>.ret, isFloatType<P.Src0VT>.ret);
let ReadsModeReg = !or(P.DstVT.isFP, P.Src0VT.isFP);

let mayRaiseFPException = ReadsModeReg;
let Uses = !if(ReadsModeReg, [MODE, EXEC], [EXEC]);
Expand Down Expand Up @@ -599,7 +599,7 @@ class VOP_SDWA_Pseudo <string opName, VOPProfile P, list<dag> pattern=[]> :
let VALU = 1;
let SDWA = 1;

let ReadsModeReg = !or(isFloatType<P.DstVT>.ret, isFloatType<P.Src0VT>.ret);
let ReadsModeReg = !or(P.DstVT.isFP, P.Src0VT.isFP);

let mayRaiseFPException = ReadsModeReg;
let Uses = !if(ReadsModeReg, [MODE, EXEC], [EXEC]);
Expand Down Expand Up @@ -811,7 +811,7 @@ class VOP_DPP_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[],
let DPP = 1;
let Size = 8;

let ReadsModeReg = !or(isFloatType<P.DstVT>.ret, isFloatType<P.Src0VT>.ret);
let ReadsModeReg = !or(P.DstVT.isFP, P.Src0VT.isFP);

let mayRaiseFPException = ReadsModeReg;
let Uses = !if(ReadsModeReg, [MODE, EXEC], [EXEC]);
Expand Down

0 comments on commit 8e9e4f8

Please sign in to comment.