Skip to content

Commit

Permalink
[RISCV] Add Sched classes for vector crypto instructions
Browse files Browse the repository at this point in the history 
The vector crypto instructions may have different scheduling behavior
compared to VALU operations. Instead of using scheduling resources that
describe VALU operations, we give these instructions their own
scheduling resources. This is similar to what we did for Zb* instructions.

The sifive-p670 has vector crypto, so we model behavior for these instructions
in the P600SchedModel. The numbers are based off of measurements collected
internally. These numbers are a bit old and new measurments show that they may
not be fully accurate. It is likley that we will refine these numbers in a
follow up patch(s) based on new measurments.
  • Loading branch information
@michaelmaitland
michaelmaitland committed Apr 25, 2024
1 parent ebd7a58 commit 90c5820
Show file tree
Hide file tree
Showing 12 changed files with 498 additions and 133 deletions.
144 changes: 110 additions & 34 deletions llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -24,9 +24,9 @@ def tuimm5 : RISCVOp, TImmLeaf<XLenVT, [{return isUInt<5>(Imm);}]>;
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
multiclass VCLMUL_MV_V_X<string opcodestr, bits<6> funct6> {
def V : VALUVV<funct6, OPMVV, opcodestr # "." # "vv">,
SchedBinaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV">;
SchedBinaryMC<"WriteVCLMUL", "ReadVCLMUL", "ReadVCLMUL">;
def X : VALUVX<funct6, OPMVX, opcodestr # "." # "vx">,
SchedBinaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV">;
SchedBinaryMC<"WriteVCLMULH", "ReadVCLMULH", "ReadVCLMULH">;
}

class RVInstIVI_VROR<bits<6> funct6, dag outs, dag ins, string opcodestr,
Expand Down Expand Up @@ -55,7 +55,7 @@ multiclass VROR_IV_V_X_I<string opcodestr, bits<6> funct6>
def I : RVInstIVI_VROR<funct6, (outs VR:$vd),
(ins VR:$vs2, uimm6:$imm, VMaskOp:$vm),
opcodestr # ".vi", "$vd, $vs2, $imm$vm">,
SchedUnaryMC<"WriteVIALUI", "ReadVIALUV">;
SchedUnaryMC<"WriteVROR", "ReadVROR">;
}

// op vd, vs2, vs1
Expand Down Expand Up @@ -107,10 +107,10 @@ multiclass VAES_MV_V_S<bits<6> funct6_vv, bits<6> funct6_vs, bits<5> vs1,
RISCVVFormat opv, string opcodestr> {
let RVVConstraint = NoConstraint in
def NAME # _VV : PALUVs2NoVmBinary<funct6_vv, vs1, opv, opcodestr # ".vv">,
SchedBinaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV">;
SchedBinaryMC<"WriteVAESMV", "ReadVAESMV", "ReadVAESMV">;
let RVVConstraint = VS2Constraint in
def NAME # _VS : PALUVs2NoVmBinary<funct6_vs, vs1, opv, opcodestr # ".vs">,
SchedBinaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV">;
SchedBinaryMC<"WriteVAESMV", "ReadVAESMV", "ReadVAESMV">;
}
} // hasSideEffects = 0, mayLoad = 0, mayStore = 0

Expand Down Expand Up @@ -142,22 +142,22 @@ let Predicates = [HasStdExtZvkb] in {

let Predicates = [HasStdExtZvkg], RVVConstraint = NoConstraint in {
def VGHSH_VV : PALUVVNoVmTernary<0b101100, OPMVV, "vghsh.vv">,
SchedTernaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV",
"ReadVIALUV">;
SchedTernaryMC<"WriteVGHSH", "ReadVGHSH", "ReadVGHSH",
"ReadVGHSH">;
def VGMUL_VV : PALUVs2NoVmBinary<0b101000, 0b10001, OPMVV, "vgmul.vv">,
SchedBinaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV">;
SchedBinaryMC<"WriteVGMUL", "ReadVGMUL", "ReadVGMUL">;
} // Predicates = [HasStdExtZvkg]

let Predicates = [HasStdExtZvknhaOrZvknhb], RVVConstraint = Sha2Constraint in {
def VSHA2CH_VV : PALUVVNoVmTernary<0b101110, OPMVV, "vsha2ch.vv">,
SchedTernaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV",
"ReadVIALUV">;
SchedTernaryMC<"WriteVSHA2CH", "ReadVSHA2CH", "ReadVSHA2CH",
"ReadVSHA2CH">;
def VSHA2CL_VV : PALUVVNoVmTernary<0b101111, OPMVV, "vsha2cl.vv">,
SchedTernaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV",
"ReadVIALUV">;
SchedTernaryMC<"WriteVSHA2CL", "ReadVSHA2CL", "ReadVSHA2CL",
"ReadVSHA2CL">;
def VSHA2MS_VV : PALUVVNoVmTernary<0b101101, OPMVV, "vsha2ms.vv">,
SchedTernaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV",
"ReadVIALUV">;
SchedTernaryMC<"WriteVSHA2MS", "ReadVSHA2MS", "ReadVSHA2MS",
"ReadVSHA2MS">;
} // Predicates = [HasStdExtZvknhaOrZvknhb]

let Predicates = [HasStdExtZvkned] in {
Expand All @@ -166,26 +166,26 @@ let Predicates = [HasStdExtZvkned] in {
defm VAESEF : VAES_MV_V_S<0b101000, 0b101001, 0b00011, OPMVV, "vaesef">;
defm VAESEM : VAES_MV_V_S<0b101000, 0b101001, 0b00010, OPMVV, "vaesem">;
def VAESKF1_VI : PALUVINoVm<0b100010, "vaeskf1.vi", uimm5>,
SchedUnaryMC<"WriteVIALUV", "ReadVIALUV">;
SchedUnaryMC<"WriteVAESKF1", "ReadVAESKF2">;
def VAESKF2_VI : PALUVINoVmBinary<0b101010, "vaeskf2.vi", uimm5>,
SchedBinaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV">;
SchedBinaryMC<"WriteVAESKF2", "ReadVAESKF2", "ReadVAESKF2">;
let RVVConstraint = VS2Constraint in
def VAESZ_VS : PALUVs2NoVmBinary<0b101001, 0b00111, OPMVV, "vaesz.vs">,
SchedBinaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV">;
SchedBinaryMC<"WriteVAESZ", "ReadVAESZ", "ReadVAESZ">;
} // Predicates = [HasStdExtZvkned]

let Predicates = [HasStdExtZvksed] in {
let RVVConstraint = NoConstraint in
def VSM4K_VI : PALUVINoVm<0b100001, "vsm4k.vi", uimm5>,
SchedUnaryMC<"WriteVIALUV", "ReadVIALUV">;
SchedUnaryMC<"WriteVSM4K", "ReadVSM4K">;
defm VSM4R : VAES_MV_V_S<0b101000, 0b101001, 0b10000, OPMVV, "vsm4r">;
} // Predicates = [HasStdExtZvksed]

let Predicates = [HasStdExtZvksh], RVVConstraint = VS2Constraint in {
def VSM3C_VI : PALUVINoVmBinary<0b101011, "vsm3c.vi", uimm5>,
SchedBinaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV">;
SchedBinaryMC<"WriteVSM3C", "ReadVSM3C", "ReadVSM3C">;
def VSM3ME_VV : PALUVVNoVm<0b100000, OPMVV, "vsm3me.vv">,
SchedUnaryMC<"WriteVIALUI", "ReadVIALUV">;
SchedUnaryMC<"WriteVSM3ME", "ReadVSM3ME">;
} // Predicates = [HasStdExtZvksh]

//===----------------------------------------------------------------------===//
Expand Down Expand Up @@ -337,10 +337,10 @@ multiclass VPseudoVCLMUL_VV_VX {
foreach m = MxList in {
defvar mx = m.MX;
defm "" : VPseudoBinaryV_VV<m>,
SchedBinary<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV", mx,
SchedBinary<"WriteVCLMUL", "ReadVCLMUL", "ReadVCLMUL", mx,
forceMergeOpRead=true>;
defm "" : VPseudoBinaryV_VX<m>,
SchedBinary<"WriteVIALUX", "ReadVIALUV", "ReadVIALUX", mx,
SchedBinary<"WriteVCLMULH", "ReadVCLMULH", "ReadVCLMULH", mx,
forceMergeOpRead=true>;
}
}
Expand All @@ -354,28 +354,104 @@ multiclass VPseudoUnaryV_V<LMULInfo m> {
}
}

multiclass VPseudoVALU_V {
multiclass VPseudoVBREV {
foreach m = MxList in {
defvar mx = m.MX;
defm "" : VPseudoUnaryV_V<m>,
SchedUnary<"WriteVIALUV", "ReadVIALUV", mx,
forceMergeOpRead=true>;
SchedUnary<"WriteVBREV", "ReadVBREV", mx, forceMergeOpRead=true>;
}
}

multiclass VPseudoVCLZ {
foreach m = MxList in {
defvar mx = m.MX;
defm "" : VPseudoUnaryV_V<m>,
SchedUnary<"WriteVCLZ", "ReadVCLZ", mx, forceMergeOpRead=true>;
}
}

multiclass VPseudoVCTZ {
foreach m = MxList in {
defvar mx = m.MX;
defm "" : VPseudoUnaryV_V<m>,
SchedUnary<"WriteVCTZ", "ReadVCTZ", mx, forceMergeOpRead=true>;
}
}

multiclass VPseudoVCPOP {
foreach m = MxList in {
defvar mx = m.MX;
defm "" : VPseudoUnaryV_V<m>,
SchedUnary<"WriteVCPOP", "ReadVCPOP", mx, forceMergeOpRead=true>;
}
}

multiclass VPseudoVWALU_VV_VX_VI<Operand ImmType> : VPseudoVWALU_VV_VX {
foreach m = MxListW in {
defm "" : VPseudoBinaryW_VI<ImmType, m>,
SchedUnary<"WriteVIWALUV", "ReadVIWALUV", m.MX,
SchedUnary<"WriteVWSLL", "ReadVWSLL", m.MX,
forceMergeOpRead=true>;
}
}

multiclass VPseudoVANDN {
foreach m = MxList in {
defm "" : VPseudoBinaryV_VV<m>,
SchedBinary<"WriteVANDN", "ReadVANDN", "ReadVANDN", m.MX,
forceMergeOpRead=true>;
defm "" : VPseudoBinaryV_VX<m>,
SchedBinary<"WriteVANDN", "ReadVANDN", "ReadVANDN", m.MX,
forceMergeOpRead=true>;
}
}

multiclass VPseudoVBREV8 {
foreach m = MxList in {
defvar mx = m.MX;
defm "" : VPseudoUnaryV_V<m>,
SchedUnary<"WriteVBREV8", "ReadVBREV8", mx, forceMergeOpRead=true>;
}
}

multiclass VPseudoVREV8 {
foreach m = MxList in {
defvar mx = m.MX;
defm "" : VPseudoUnaryV_V<m>,
SchedUnary<"WriteVREV8", "ReadVREV8", mx, forceMergeOpRead=true>;
}
}

multiclass VPseudoVROL {
foreach m = MxList in {
defm "" : VPseudoBinaryV_VV<m>,
SchedBinary<"WriteVROL", "ReadVROL", "ReadVROL", m.MX,
forceMergeOpRead=true>;
defm "" : VPseudoBinaryV_VX<m>,
SchedBinary<"WriteVROL", "ReadVROL", "ReadVROL", m.MX,
forceMergeOpRead=true>;
}
}

multiclass VPseudoVROR<Operand ImmType> {
defvar Constraint = "";
foreach m = MxList in {
defvar mx = m.MX;
defm "" : VPseudoBinaryV_VV<m>,
SchedBinary<"WriteVROR", "ReadVROR", "ReadVROR", mx,
forceMergeOpRead=true>;
defm "" : VPseudoBinaryV_VX<m>,
SchedBinary<"WriteVROR", "ReadVROR", "ReadVROR", mx,
forceMergeOpRead=true>;
defm "" : VPseudoBinaryV_VI<ImmType, m>,
SchedUnary<"WriteVROR", "ReadVROR", mx, forceMergeOpRead=true>;
}
}

let Predicates = [HasStdExtZvbb] in {
defm PseudoVBREV : VPseudoVALU_V;
defm PseudoVCLZ : VPseudoVALU_V;
defm PseudoVCTZ : VPseudoVALU_V;
defm PseudoVCPOP : VPseudoVALU_V;
defm PseudoVBREV : VPseudoVBREV;
defm PseudoVCLZ : VPseudoVCLZ;
defm PseudoVCTZ : VPseudoVCTZ;
defm PseudoVCPOP : VPseudoVCPOP;
defm PseudoVWSLL : VPseudoVWALU_VV_VX_VI<uimm5>;
} // Predicates = [HasStdExtZvbb]

Expand All @@ -385,10 +461,10 @@ let Predicates = [HasStdExtZvbc] in {
} // Predicates = [HasStdExtZvbc]

let Predicates = [HasStdExtZvkb] in {
defm PseudoVANDN : VPseudoVALU_VV_VX;
defm PseudoVBREV8 : VPseudoVALU_V;
defm PseudoVREV8 : VPseudoVALU_V;
defm PseudoVROL : VPseudoVALU_VV_VX;
defm PseudoVANDN : VPseudoVANDN;
defm PseudoVBREV8 : VPseudoVBREV8;
defm PseudoVREV8 : VPseudoVREV8;
defm PseudoVROL : VPseudoVROL;
defm PseudoVROR : VPseudoVALU_VV_VX_VI<uimm6>;
} // Predicates = [HasStdExtZvkb]

Expand Down
1 change: 1 addition & 0 deletions llvm/lib/Target/RISCV/RISCVSchedRocket.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -262,4 +262,5 @@ defm : UnsupportedSchedZfa;
defm : UnsupportedSchedZfh;
defm : UnsupportedSchedSFB;
defm : UnsupportedSchedXsfvcp;
defm : UnsupportedSchedZvk;
}
1 change: 1 addition & 0 deletions llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1298,4 +1298,5 @@ defm : UnsupportedSchedZbc;
defm : UnsupportedSchedZbkb;
defm : UnsupportedSchedZbkx;
defm : UnsupportedSchedZfa;
defm : UnsupportedSchedZvk;
}
1 change: 1 addition & 0 deletions llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -367,4 +367,5 @@ defm : UnsupportedSchedSFB;
defm : UnsupportedSchedZfa;
defm : UnsupportedSchedV;
defm : UnsupportedSchedXsfvcp;
defm : UnsupportedSchedZvk;
}
81 changes: 81 additions & 0 deletions llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -748,6 +748,60 @@ foreach mx = SchedMxList in {
}
}

// Vector Crypto
foreach mx = SchedMxList in {
defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;
defvar IsWorstCase = SiFiveP600IsWorstCaseMX<mx, SchedMxList>.c;
// Zvbb
let Latency = 2, ReleaseAtCycles = [LMulLat] in {
defm "" : LMULWriteResMX<"WriteVBREV", [SiFiveP600VectorArith], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVCLZ", [SiFiveP600VectorArith], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVCPOP", [SiFiveP600VectorArith], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVCTZ", [SiFiveP600VectorArith], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVWSLL", [SiFiveP600VectorArith], mx, IsWorstCase>;
}
// Zvbc
let Latency = 2, ReleaseAtCycles = [LMulLat] in {
defm "" : LMULWriteResMX<"WriteVCLMUL", [SiFiveP600VectorArith], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVCLMULH", [SiFiveP600VectorArith], mx, IsWorstCase>;
}
// Zvkb
let Latency = 1, ReleaseAtCycles = [LMulLat] in
defm "" : LMULWriteResMX<"WriteVANDN", [SiFiveP600VectorArith], mx, IsWorstCase>;
let Latency = 2, ReleaseAtCycles = [LMulLat] in {
defm "" : LMULWriteResMX<"WriteVBREV8", [SiFiveP600VectorArith], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVREV8", [SiFiveP600VectorArith], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVROL", [SiFiveP600VectorArith], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVROR", [SiFiveP600VectorArith], mx, IsWorstCase>;
}
// Zvkg
let Latency = 2, ReleaseAtCycles = [LMulLat] in {
defm "" : LMULWriteResMX<"WriteVGHSH", [SiFiveP600VectorArith], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVGMUL", [SiFiveP600VectorArith], mx, IsWorstCase>;
}
// ZvknhaOrZvknhb
let Latency = 3, ReleaseAtCycles = [LMulLat] in {
defm "" : LMULWriteResMX<"WriteVSHA2CH", [SiFiveP600VectorArith], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVSHA2CL", [SiFiveP600VectorArith], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVSHA2MS", [SiFiveP600VectorArith], mx, IsWorstCase>;
}
// Zvkned
let Latency = 2, ReleaseAtCycles = [LMulLat] in {
defm "" : LMULWriteResMX<"WriteVAESMV", [SiFiveP600VectorArith], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVAESKF1", [SiFiveP600VectorArith], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVAESKF2", [SiFiveP600VectorArith], mx, IsWorstCase>;
}
let Latency = 1, ReleaseAtCycles = [LMulLat] in
defm "" : LMULWriteResMX<"WriteVAESZ", [SiFiveP600VectorArith], mx, IsWorstCase>;
// Zvksed
let Latency = 3, ReleaseAtCycles = [LMulLat] in {
defm "" : LMULWriteResMX<"WriteVSM4K", [SiFiveP600VEXQ0], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVSM4R", [SiFiveP600VEXQ0], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVSM3C", [SiFiveP600VEXQ0], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVSM3ME", [SiFiveP600VEXQ0], mx, IsWorstCase>;
}
}

// Others
def : WriteRes<WriteCSR, [SiFiveP600SYS]>;
def : WriteRes<WriteNop, []>;
Expand Down Expand Up @@ -1032,6 +1086,33 @@ foreach mx = SchedMxList in {
def : ReadAdvance<!cast<SchedRead>("ReadVMergeOp_" # mx # "_E" # sew), 0>;
}

// Vector Crypto Extensions
defm "" : LMULReadAdvance<"ReadVBREV", 0>;
defm "" : LMULReadAdvance<"ReadVCLZ", 0>;
defm "" : LMULReadAdvance<"ReadVCPOP", 0>;
defm "" : LMULReadAdvance<"ReadVCTZ", 0>;
defm "" : LMULReadAdvance<"ReadVWSLL", 0>;
defm "" : LMULReadAdvance<"ReadVCLMUL", 0>;
defm "" : LMULReadAdvance<"ReadVCLMULH", 0>;
defm "" : LMULReadAdvance<"ReadVANDN", 0>;
defm "" : LMULReadAdvance<"ReadVBREV8", 0>;
defm "" : LMULReadAdvance<"ReadVREV8", 0>;
defm "" : LMULReadAdvance<"ReadVROL", 0>;
defm "" : LMULReadAdvance<"ReadVROR", 0>;
defm "" : LMULReadAdvance<"ReadVGHSH", 0>;
defm "" : LMULReadAdvance<"ReadVGMUL", 0>;
defm "" : LMULReadAdvance<"ReadVSHA2CH", 0>;
defm "" : LMULReadAdvance<"ReadVSHA2CL", 0>;
defm "" : LMULReadAdvance<"ReadVSHA2MS", 0>;
defm "" : LMULReadAdvance<"ReadVAESMV", 0>;
defm "" : LMULReadAdvance<"ReadVAESKF1", 0>;
defm "" : LMULReadAdvance<"ReadVAESKF2", 0>;
defm "" : LMULReadAdvance<"ReadVAESZ", 0>;
defm "" : LMULReadAdvance<"ReadVSM4K", 0>;
defm "" : LMULReadAdvance<"ReadVSM4R", 0>;
defm "" : LMULReadAdvance<"ReadVSM3C", 0>;
defm "" : LMULReadAdvance<"ReadVSM3ME", 0>;

//===----------------------------------------------------------------------===//
// Unsupported extensions
defm : UnsupportedSchedZabha;
Expand Down
1 change: 1 addition & 0 deletions llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -213,4 +213,5 @@ defm : UnsupportedSchedZbkx;
defm : UnsupportedSchedZfa;
defm : UnsupportedSchedZfh;
defm : UnsupportedSchedXsfvcp;
defm : UnsupportedSchedZvk;
}
1 change: 1 addition & 0 deletions llvm/lib/Target/RISCV/RISCVSchedXiangShanNanHu.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -312,4 +312,5 @@ defm : UnsupportedSchedZfh;
defm : UnsupportedSchedSFB;
defm : UnsupportedSchedZabha;
defm : UnsupportedSchedXsfvcp;
defm : UnsupportedSchedZvk;
}
1 change: 1 addition & 0 deletions llvm/lib/Target/RISCV/RISCVSchedule.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -297,3 +297,4 @@ def : ReadAdvance<ReadAtomicHD, 0>;
include "RISCVScheduleZb.td"
include "RISCVScheduleV.td"
include "RISCVScheduleXSf.td"
include "RISCVScheduleZvk.td"
Loading

0 comments on commit 90c5820

Please sign in to comment.