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CodeGen: Reorder case handling for is.fpclass legalization
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Subnormal and zero checks can be combined into one, so move
the code closer to reduce the diff in a future change.
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@arsenm
arsenm committed Mar 17, 2023
1 parent 0eac3c5 commit 9356ec1
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Showing 4 changed files with 138 additions and 133 deletions.
28 changes: 14 additions & 14 deletions llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
View file
Expand Up @@ -7438,6 +7438,20 @@ LegalizerHelper::lowerISFPCLASS(MachineInstr &MI) {
AsInt, SignBitC));
}

if (FPClassTest PartialCheck = Mask & fcSubnormal) {
// issubnormal(V) ==> unsigned(abs(V) - 1) u< (all mantissa bits set)
// issubnormal(V) && V>0 ==> unsigned(V - 1) u< (all mantissa bits set)
auto V = (PartialCheck == fcPosSubnormal) ? AsInt : Abs;
auto OneC = MIRBuilder.buildConstant(IntTy, 1);
auto VMinusOne = MIRBuilder.buildSub(IntTy, V, OneC);
auto SubnormalRes =
MIRBuilder.buildICmp(CmpInst::Predicate::ICMP_ULT, DstTy, VMinusOne,
MIRBuilder.buildConstant(IntTy, AllOneMantissa));
if (PartialCheck == fcNegSubnormal)
SubnormalRes = MIRBuilder.buildAnd(DstTy, SubnormalRes, Sign);
appendToRes(SubnormalRes);
}

if (FPClassTest PartialCheck = Mask & fcInf) {
if (PartialCheck == fcPosInf)
appendToRes(MIRBuilder.buildICmp(CmpInst::Predicate::ICMP_EQ, DstTy,
Expand Down Expand Up @@ -7474,20 +7488,6 @@ LegalizerHelper::lowerISFPCLASS(MachineInstr &MI) {
}
}

if (FPClassTest PartialCheck = Mask & fcSubnormal) {
// issubnormal(V) ==> unsigned(abs(V) - 1) u< (all mantissa bits set)
// issubnormal(V) && V>0 ==> unsigned(V - 1) u< (all mantissa bits set)
auto V = (PartialCheck == fcPosSubnormal) ? AsInt : Abs;
auto OneC = MIRBuilder.buildConstant(IntTy, 1);
auto VMinusOne = MIRBuilder.buildSub(IntTy, V, OneC);
auto SubnormalRes =
MIRBuilder.buildICmp(CmpInst::Predicate::ICMP_ULT, DstTy, VMinusOne,
MIRBuilder.buildConstant(IntTy, AllOneMantissa));
if (PartialCheck == fcNegSubnormal)
SubnormalRes = MIRBuilder.buildAnd(DstTy, SubnormalRes, Sign);
appendToRes(SubnormalRes);
}

if (FPClassTest PartialCheck = Mask & fcNormal) {
// isnormal(V) ==> (0 u< exp u< max_exp) ==> (unsigned(exp-1) u<
// (max_exp-1))
Expand Down
26 changes: 13 additions & 13 deletions llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
View file
Expand Up @@ -8149,6 +8149,19 @@ SDValue TargetLowering::expandIS_FPCLASS(EVT ResultVT, SDValue Op,
appendResult(PartialRes);
}

if (unsigned PartialCheck = Test & fcSubnormal) {
// issubnormal(V) ==> unsigned(abs(V) - 1) < (all mantissa bits set)
// issubnormal(V) && V>0 ==> unsigned(V - 1) < (all mantissa bits set)
SDValue V = (PartialCheck == fcPosSubnormal) ? OpAsInt : AbsV;
SDValue MantissaV = DAG.getConstant(AllOneMantissa, DL, IntVT);
SDValue VMinusOneV =
DAG.getNode(ISD::SUB, DL, IntVT, V, DAG.getConstant(1, DL, IntVT));
PartialRes = DAG.getSetCC(DL, ResultVT, VMinusOneV, MantissaV, ISD::SETULT);
if (PartialCheck == fcNegSubnormal)
PartialRes = DAG.getNode(ISD::AND, DL, ResultVT, PartialRes, SignV);
appendResult(PartialRes);
}

if (unsigned PartialCheck = Test & fcInf) {
if (PartialCheck == fcPosInf)
PartialRes = DAG.getSetCC(DL, ResultVT, OpAsInt, InfV, ISD::SETEQ);
Expand Down Expand Up @@ -8193,19 +8206,6 @@ SDValue TargetLowering::expandIS_FPCLASS(EVT ResultVT, SDValue Op,
appendResult(PartialRes);
}

if (unsigned PartialCheck = Test & fcSubnormal) {
// issubnormal(V) ==> unsigned(abs(V) - 1) < (all mantissa bits set)
// issubnormal(V) && V>0 ==> unsigned(V - 1) < (all mantissa bits set)
SDValue V = (PartialCheck == fcPosSubnormal) ? OpAsInt : AbsV;
SDValue MantissaV = DAG.getConstant(AllOneMantissa, DL, IntVT);
SDValue VMinusOneV =
DAG.getNode(ISD::SUB, DL, IntVT, V, DAG.getConstant(1, DL, IntVT));
PartialRes = DAG.getSetCC(DL, ResultVT, VMinusOneV, MantissaV, ISD::SETULT);
if (PartialCheck == fcNegSubnormal)
PartialRes = DAG.getNode(ISD::AND, DL, ResultVT, PartialRes, SignV);
appendResult(PartialRes);
}

if (unsigned PartialCheck = Test & fcNormal) {
// isnormal(V) ==> (0 < exp < max_exp) ==> (unsigned(exp-1) < (max_exp-1))
APInt ExpLSB = ExpMask & ~(ExpMask.shl(1));
Expand Down
156 changes: 78 additions & 78 deletions llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
View file
Expand Up @@ -1758,16 +1758,16 @@ define i1 @not_isnormal_f16(half %x) {
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
; GFX7GLISEL-NEXT: v_bfe_u32 v1, v0, 0, 16
; GFX7GLISEL-NEXT: s_movk_i32 s6, 0x7c00
; GFX7GLISEL-NEXT: v_subrev_i32_e64 v0, s[4:5], 1, v0
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x3ff
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], s6, v1
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e64 s[4:5], v0, v2
; GFX7GLISEL-NEXT: s_movk_i32 s6, 0x7c00
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, s6, v1
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, s6, v1
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], s[4:5], vcc
; GFX7GLISEL-NEXT: v_subrev_i32_e32 v0, vcc, 1, v0
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x3ff
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, s6, v1
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], s[4:5], vcc
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
Expand Down Expand Up @@ -1827,19 +1827,19 @@ define i1 @not_is_plus_normal_f16(half %x) {
; GFX7GLISEL: ; %bb.0:
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0x7fff, v0
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7GLISEL-NEXT: v_bfe_u32 v2, v1, 0, 16
; GFX7GLISEL-NEXT: s_movk_i32 s8, 0x7c00
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[6:7], s8, v2
; GFX7GLISEL-NEXT: v_cmp_ne_u32_e64 s[4:5], v0, v2
; GFX7GLISEL-NEXT: v_subrev_i32_e64 v0, s[6:7], 1, v1
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7GLISEL-NEXT: v_mov_b32_e32 v3, 0x3ff
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e64 s[6:7], v0, v3
; GFX7GLISEL-NEXT: s_movk_i32 s8, 0x7c00
; GFX7GLISEL-NEXT: s_or_b64 s[6:7], vcc, s[6:7]
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, s8, v2
; GFX7GLISEL-NEXT: v_cmp_ne_u32_e64 s[4:5], v0, v2
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, s8, v2
; GFX7GLISEL-NEXT: s_or_b64 s[6:7], s[6:7], vcc
; GFX7GLISEL-NEXT: v_subrev_i32_e32 v0, vcc, 1, v1
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x3ff
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v2
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, s8, v2
; GFX7GLISEL-NEXT: s_or_b64 s[6:7], s[6:7], vcc
; GFX7GLISEL-NEXT: v_subrev_i32_e32 v0, vcc, 0x400, v1
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
Expand Down Expand Up @@ -1905,19 +1905,19 @@ define i1 @not_is_neg_normal_f16(half %x) {
; GFX7GLISEL: ; %bb.0:
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0x7fff, v0
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7GLISEL-NEXT: v_bfe_u32 v2, v1, 0, 16
; GFX7GLISEL-NEXT: s_movk_i32 s8, 0x7c00
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[6:7], s8, v2
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v0, v2
; GFX7GLISEL-NEXT: v_subrev_i32_e64 v0, s[6:7], 1, v1
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7GLISEL-NEXT: v_mov_b32_e32 v3, 0x3ff
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e64 s[6:7], v0, v3
; GFX7GLISEL-NEXT: s_movk_i32 s8, 0x7c00
; GFX7GLISEL-NEXT: s_or_b64 s[6:7], vcc, s[6:7]
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, s8, v2
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v0, v2
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, s8, v2
; GFX7GLISEL-NEXT: s_or_b64 s[6:7], s[6:7], vcc
; GFX7GLISEL-NEXT: v_subrev_i32_e32 v0, vcc, 1, v1
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x3ff
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v2
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, s8, v2
; GFX7GLISEL-NEXT: s_or_b64 s[6:7], s[6:7], vcc
; GFX7GLISEL-NEXT: v_subrev_i32_e32 v0, vcc, 0x400, v1
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
Expand Down Expand Up @@ -2155,15 +2155,15 @@ define i1 @not_iszero_f16(half %x) {
; GFX7GLISEL: ; %bb.0:
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
; GFX7GLISEL-NEXT: v_bfe_u32 v1, v0, 0, 16
; GFX7GLISEL-NEXT: s_movk_i32 s4, 0x7c00
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, s4, v1
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e64 s[4:5], s4, v1
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GFX7GLISEL-NEXT: v_subrev_i32_e32 v1, vcc, 1, v0
; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x3ff
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v1, v2
; GFX7GLISEL-NEXT: v_bfe_u32 v1, v0, 0, 16
; GFX7GLISEL-NEXT: s_movk_i32 s6, 0x7c00
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], s6, v1
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, s6, v1
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], s[4:5], vcc
; GFX7GLISEL-NEXT: v_subrev_i32_e32 v0, vcc, 0x400, v0
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
Expand Down Expand Up @@ -2659,7 +2659,7 @@ define i1 @not_iszero_or_nan_f16(half %x) {
; GFX7SELDAG-NEXT: v_add_i32_e64 v1, s[4:5], -1, v0
; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x3ff
; GFX7SELDAG-NEXT: v_cmp_gt_u32_e64 s[4:5], s4, v1
; GFX7SELDAG-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GFX7SELDAG-NEXT: s_or_b64 s[4:5], s[4:5], vcc
; GFX7SELDAG-NEXT: v_add_i32_e32 v0, vcc, 0xfffffc00, v0
; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7SELDAG-NEXT: v_cmp_gt_u32_e32 vcc, s6, v0
Expand All @@ -2671,13 +2671,13 @@ define i1 @not_iszero_or_nan_f16(half %x) {
; GFX7GLISEL: ; %bb.0: ; %entry
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
; GFX7GLISEL-NEXT: v_bfe_u32 v1, v0, 0, 16
; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x7c00
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2
; GFX7GLISEL-NEXT: v_subrev_i32_e64 v1, s[4:5], 1, v0
; GFX7GLISEL-NEXT: v_subrev_i32_e32 v1, vcc, 1, v0
; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x3ff
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e64 s[4:5], v1, v2
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v1, v2
; GFX7GLISEL-NEXT: v_bfe_u32 v1, v0, 0, 16
; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x7c00
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v1, v2
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GFX7GLISEL-NEXT: v_subrev_i32_e32 v0, vcc, 0x400, v0
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
Expand Down Expand Up @@ -2735,7 +2735,7 @@ define i1 @not_iszero_or_nan_f_daz(half %x) #0 {
; GFX7SELDAG-NEXT: v_add_i32_e64 v1, s[4:5], -1, v0
; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x3ff
; GFX7SELDAG-NEXT: v_cmp_gt_u32_e64 s[4:5], s4, v1
; GFX7SELDAG-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GFX7SELDAG-NEXT: s_or_b64 s[4:5], s[4:5], vcc
; GFX7SELDAG-NEXT: v_add_i32_e32 v0, vcc, 0xfffffc00, v0
; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7SELDAG-NEXT: v_cmp_gt_u32_e32 vcc, s6, v0
Expand All @@ -2747,13 +2747,13 @@ define i1 @not_iszero_or_nan_f_daz(half %x) #0 {
; GFX7GLISEL: ; %bb.0: ; %entry
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
; GFX7GLISEL-NEXT: v_bfe_u32 v1, v0, 0, 16
; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x7c00
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2
; GFX7GLISEL-NEXT: v_subrev_i32_e64 v1, s[4:5], 1, v0
; GFX7GLISEL-NEXT: v_subrev_i32_e32 v1, vcc, 1, v0
; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x3ff
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e64 s[4:5], v1, v2
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v1, v2
; GFX7GLISEL-NEXT: v_bfe_u32 v1, v0, 0, 16
; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x7c00
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v1, v2
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GFX7GLISEL-NEXT: v_subrev_i32_e32 v0, vcc, 0x400, v0
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
Expand Down Expand Up @@ -2811,7 +2811,7 @@ define i1 @not_iszero_or_nan_f_maybe_daz(half %x) #1 {
; GFX7SELDAG-NEXT: v_add_i32_e64 v1, s[4:5], -1, v0
; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x3ff
; GFX7SELDAG-NEXT: v_cmp_gt_u32_e64 s[4:5], s4, v1
; GFX7SELDAG-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GFX7SELDAG-NEXT: s_or_b64 s[4:5], s[4:5], vcc
; GFX7SELDAG-NEXT: v_add_i32_e32 v0, vcc, 0xfffffc00, v0
; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7SELDAG-NEXT: v_cmp_gt_u32_e32 vcc, s6, v0
Expand All @@ -2823,13 +2823,13 @@ define i1 @not_iszero_or_nan_f_maybe_daz(half %x) #1 {
; GFX7GLISEL: ; %bb.0: ; %entry
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
; GFX7GLISEL-NEXT: v_bfe_u32 v1, v0, 0, 16
; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x7c00
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2
; GFX7GLISEL-NEXT: v_subrev_i32_e64 v1, s[4:5], 1, v0
; GFX7GLISEL-NEXT: v_subrev_i32_e32 v1, vcc, 1, v0
; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x3ff
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e64 s[4:5], v1, v2
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v1, v2
; GFX7GLISEL-NEXT: v_bfe_u32 v1, v0, 0, 16
; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x7c00
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v1, v2
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GFX7GLISEL-NEXT: v_subrev_i32_e32 v0, vcc, 0x400, v0
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
Expand Down Expand Up @@ -3009,18 +3009,18 @@ define i1 @not_iszero_or_qnan_f16(half %x) {
; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x7e00
; GFX7SELDAG-NEXT: s_movk_i32 s6, 0x7c00
; GFX7SELDAG-NEXT: s_movk_i32 s8, 0x7c00
; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
; GFX7SELDAG-NEXT: v_cmp_gt_i32_e32 vcc, s4, v0
; GFX7SELDAG-NEXT: v_cmp_lt_i32_e64 s[4:5], s6, v0
; GFX7SELDAG-NEXT: s_and_b64 s[4:5], s[4:5], vcc
; GFX7SELDAG-NEXT: v_cmp_eq_u32_e32 vcc, s6, v0
; GFX7SELDAG-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GFX7SELDAG-NEXT: v_add_i32_e32 v1, vcc, -1, v0
; GFX7SELDAG-NEXT: s_movk_i32 s6, 0x3ff
; GFX7SELDAG-NEXT: v_cmp_gt_u32_e32 vcc, s6, v1
; GFX7SELDAG-NEXT: v_cmp_lt_i32_e64 s[4:5], s8, v0
; GFX7SELDAG-NEXT: s_and_b64 s[6:7], s[4:5], vcc
; GFX7SELDAG-NEXT: v_add_i32_e64 v1, s[4:5], -1, v0
; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x3ff
; GFX7SELDAG-NEXT: v_cmp_eq_u32_e32 vcc, s8, v0
; GFX7SELDAG-NEXT: v_cmp_gt_u32_e64 s[4:5], s4, v1
; GFX7SELDAG-NEXT: s_or_b64 s[4:5], s[4:5], vcc
; GFX7SELDAG-NEXT: v_add_i32_e32 v0, vcc, 0xfffffc00, v0
; GFX7SELDAG-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7]
; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7SELDAG-NEXT: s_movk_i32 s6, 0x7800
; GFX7SELDAG-NEXT: v_cmp_gt_u32_e32 vcc, s6, v0
Expand All @@ -3032,22 +3032,22 @@ define i1 @not_iszero_or_qnan_f16(half %x) {
; GFX7GLISEL: ; %bb.0: ; %entry
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
; GFX7GLISEL-NEXT: v_bfe_u32 v1, v0, 0, 16
; GFX7GLISEL-NEXT: s_movk_i32 s4, 0x7c00
; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x7e00
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, s4, v1
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e64 s[4:5], s4, v1
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e64 s[6:7], v1, v2
; GFX7GLISEL-NEXT: s_and_b64 s[4:5], s[4:5], s[6:7]
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GFX7GLISEL-NEXT: v_subrev_i32_e32 v1, vcc, 1, v0
; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x3ff
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v1, v2
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], s[4:5], vcc
; GFX7GLISEL-NEXT: v_bfe_u32 v1, v0, 0, 16
; GFX7GLISEL-NEXT: s_movk_i32 s8, 0x7c00
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], s8, v1
; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x7e00
; GFX7GLISEL-NEXT: s_or_b64 s[6:7], vcc, s[4:5]
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, s8, v1
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e64 s[4:5], v1, v2
; GFX7GLISEL-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
; GFX7GLISEL-NEXT: v_subrev_i32_e32 v0, vcc, 0x400, v0
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7800
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], s[6:7], s[4:5]
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], s[4:5], vcc
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
Expand Down Expand Up @@ -3094,15 +3094,15 @@ define i1 @not_iszero_or_snan_f16(half %x) {
; GFX7SELDAG: ; %bb.0: ; %entry
; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x7dff
; GFX7SELDAG-NEXT: s_movk_i32 s5, 0x7c00
; GFX7SELDAG-NEXT: s_movk_i32 s6, 0x3ff
; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x7c00
; GFX7SELDAG-NEXT: s_movk_i32 s6, 0x7dff
; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
; GFX7SELDAG-NEXT: v_cmp_lt_i32_e32 vcc, s4, v0
; GFX7SELDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], s5, v0
; GFX7SELDAG-NEXT: v_cmp_eq_u32_e32 vcc, s4, v0
; GFX7SELDAG-NEXT: v_add_i32_e64 v1, s[4:5], -1, v0
; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x3ff
; GFX7SELDAG-NEXT: v_cmp_gt_u32_e64 s[4:5], s4, v1
; GFX7SELDAG-NEXT: s_or_b64 s[4:5], s[4:5], vcc
; GFX7SELDAG-NEXT: v_add_i32_e32 v1, vcc, -1, v0
; GFX7SELDAG-NEXT: v_cmp_gt_u32_e32 vcc, s6, v1
; GFX7SELDAG-NEXT: v_cmp_lt_i32_e32 vcc, s6, v0
; GFX7SELDAG-NEXT: s_or_b64 s[4:5], s[4:5], vcc
; GFX7SELDAG-NEXT: v_add_i32_e32 v0, vcc, 0xfffffc00, v0
; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0xffff, v0
Expand All @@ -3116,16 +3116,16 @@ define i1 @not_iszero_or_snan_f16(half %x) {
; GFX7GLISEL: ; %bb.0: ; %entry
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
; GFX7GLISEL-NEXT: v_bfe_u32 v1, v0, 0, 16
; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x7c00
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2
; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x7e00
; GFX7GLISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v1, v2
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GFX7GLISEL-NEXT: v_subrev_i32_e32 v1, vcc, 1, v0
; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x3ff
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v1, v2
; GFX7GLISEL-NEXT: v_bfe_u32 v1, v0, 0, 16
; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x7c00
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v1, v2
; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x7e00
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GFX7GLISEL-NEXT: v_cmp_ge_u32_e32 vcc, v1, v2
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], s[4:5], vcc
; GFX7GLISEL-NEXT: v_subrev_i32_e32 v0, vcc, 0x400, v0
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
Expand Down

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