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[mips] Range check uimm4_ptr, remove uimm6_ptr, and use correctly siz…
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…ed immediates in MSA copy/insert.

Reviewers: vkalintiris

Subscribers: dsanders, llvm-commits

Differential Revision: http://reviews.llvm.org/D18142

llvm-svn: 264052
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@dsandersllvm
dsandersllvm committed Mar 22, 2016
1 parent 07ac2bd commit 93fa4ce
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Showing 3 changed files with 74 additions and 42 deletions.
7 changes: 7 additions & 0 deletions llvm/lib/Target/Mips/MipsInstrInfo.td
View file
Expand Up @@ -709,6 +709,13 @@ def uimm5_64_report_uimm6 : Operand<i64> {
let ParserMatchClass = ConstantUImm5ReportUImm6AsmOperandClass;
}

foreach I = {1, 2, 3, 4} in
def uimm # I # _ptr : Operand<iPTR> {
let PrintMethod = "printUImm<" # I # ">";
let ParserMatchClass =
!cast<AsmOperandClass>("ConstantUImm" # I # "AsmOperandClass");
}

// Signed operands
foreach I = {4} in
def simm # I : Operand<i32> {
Expand Down
87 changes: 45 additions & 42 deletions llvm/lib/Target/Mips/MipsMSAInstrInfo.td
View file
Expand Up @@ -65,19 +65,11 @@ def MipsVExtractZExt : SDNode<"MipsISD::VEXTRACT_ZEXT_ELT",

def immZExt1Ptr : ImmLeaf<iPTR, [{return isUInt<1>(Imm);}]>;
def immZExt2Ptr : ImmLeaf<iPTR, [{return isUInt<2>(Imm);}]>;
def immZExt3Ptr : ImmLeaf<iPTR, [{return isUInt<3>(Imm);}]>;
def immZExt4Ptr : ImmLeaf<iPTR, [{return isUInt<4>(Imm);}]>;
def immZExt6Ptr : ImmLeaf<iPTR, [{return isUInt<6>(Imm);}]>;

// Operands

def uimm4_ptr : Operand<iPTR> {
let PrintMethod = "printUImm<8>";
}

def uimm6_ptr : Operand<iPTR> {
let PrintMethod = "printUImm<8>";
}

def simm5 : Operand<i32>;

def vsplat_uimm1 : Operand<vAny> {
Expand Down Expand Up @@ -1225,13 +1217,13 @@ class MSA_BIT_SPLAT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
}

class MSA_COPY_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
ValueType VecTy, RegisterOperand ROD,
RegisterOperand ROWS,
ValueType VecTy, Operand ImmOp, ImmLeaf Imm,
RegisterOperand ROD, RegisterOperand ROWS,
InstrItinClass itin = NoItinerary> {
dag OutOperandList = (outs ROD:$rd);
dag InOperandList = (ins ROWS:$ws, uimm4_ptr:$n);
dag InOperandList = (ins ROWS:$ws, ImmOp:$n);
string AsmString = !strconcat(instr_asm, "\t$rd, $ws[$n]");
list<dag> Pattern = [(set ROD:$rd, (OpNode (VecTy ROWS:$ws), immZExt4Ptr:$n))];
list<dag> Pattern = [(set ROD:$rd, (OpNode (VecTy ROWS:$ws), Imm:$n))];
InstrItinClass Itinerary = itin;
}

Expand All @@ -1249,9 +1241,10 @@ class MSA_ELM_SLD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
}

class MSA_COPY_PSEUDO_BASE<SDPatternOperator OpNode, ValueType VecTy,
RegisterClass RCD, RegisterClass RCWS> :
MSAPseudo<(outs RCD:$wd), (ins RCWS:$ws, uimm4_ptr:$n),
[(set RCD:$wd, (OpNode (VecTy RCWS:$ws), immZExt4Ptr:$n))]> {
Operand ImmOp, ImmLeaf Imm, RegisterClass RCD,
RegisterClass RCWS> :
MSAPseudo<(outs RCD:$wd), (ins RCWS:$ws, ImmOp:$n),
[(set RCD:$wd, (OpNode (VecTy RCWS:$ws), Imm:$n))]> {
bit usesCustomInserter = 1;
}

Expand Down Expand Up @@ -1433,23 +1426,22 @@ class MSA_CBRANCH_DESC_BASE<string instr_asm, RegisterOperand ROWD> {
}

class MSA_INSERT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
RegisterOperand ROWD, RegisterOperand ROS,
Operand ImmOp, ImmLeaf Imm, RegisterOperand ROWD,
RegisterOperand ROS,
InstrItinClass itin = NoItinerary> {
dag OutOperandList = (outs ROWD:$wd);
dag InOperandList = (ins ROWD:$wd_in, ROS:$rs, uimm6_ptr:$n);
dag InOperandList = (ins ROWD:$wd_in, ROS:$rs, ImmOp:$n);
string AsmString = !strconcat(instr_asm, "\t$wd[$n], $rs");
list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in,
ROS:$rs,
immZExt6Ptr:$n))];
list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROS:$rs, Imm:$n))];
InstrItinClass Itinerary = itin;
string Constraints = "$wd = $wd_in";
}

class MSA_INSERT_PSEUDO_BASE<SDPatternOperator OpNode, ValueType Ty,
RegisterOperand ROWD, RegisterOperand ROFS> :
MSAPseudo<(outs ROWD:$wd), (ins ROWD:$wd_in, uimm6_ptr:$n, ROFS:$fs),
[(set ROWD:$wd, (OpNode (Ty ROWD:$wd_in), ROFS:$fs,
immZExt6Ptr:$n))]> {
Operand ImmOp, ImmLeaf Imm, RegisterOperand ROWD,
RegisterOperand ROFS> :
MSAPseudo<(outs ROWD:$wd), (ins ROWD:$wd_in, ImmOp:$n, ROFS:$fs),
[(set ROWD:$wd, (OpNode (Ty ROWD:$wd_in), ROFS:$fs, Imm:$n))]> {
bit usesCustomInserter = 1;
string Constraints = "$wd = $wd_in";
}
Expand Down Expand Up @@ -1867,24 +1859,33 @@ class CLTI_U_D_DESC : MSA_I5_DESC_BASE<"clti_u.d", vsetult_v2i64,
vsplati64_uimm5, MSA128DOpnd>;

class COPY_S_B_DESC : MSA_COPY_DESC_BASE<"copy_s.b", vextract_sext_i8, v16i8,
GPR32Opnd, MSA128BOpnd>;
uimm4_ptr, immZExt4Ptr, GPR32Opnd,
MSA128BOpnd>;
class COPY_S_H_DESC : MSA_COPY_DESC_BASE<"copy_s.h", vextract_sext_i16, v8i16,
GPR32Opnd, MSA128HOpnd>;
uimm3_ptr, immZExt3Ptr, GPR32Opnd,
MSA128HOpnd>;
class COPY_S_W_DESC : MSA_COPY_DESC_BASE<"copy_s.w", vextract_sext_i32, v4i32,
GPR32Opnd, MSA128WOpnd>;
uimm2_ptr, immZExt2Ptr, GPR32Opnd,
MSA128WOpnd>;
class COPY_S_D_DESC : MSA_COPY_DESC_BASE<"copy_s.d", vextract_sext_i64, v2i64,
GPR64Opnd, MSA128DOpnd>;
uimm1_ptr, immZExt1Ptr, GPR64Opnd,
MSA128DOpnd>;

class COPY_U_B_DESC : MSA_COPY_DESC_BASE<"copy_u.b", vextract_zext_i8, v16i8,
GPR32Opnd, MSA128BOpnd>;
uimm4_ptr, immZExt4Ptr, GPR32Opnd,
MSA128BOpnd>;
class COPY_U_H_DESC : MSA_COPY_DESC_BASE<"copy_u.h", vextract_zext_i16, v8i16,
GPR32Opnd, MSA128HOpnd>;
uimm3_ptr, immZExt3Ptr, GPR32Opnd,
MSA128HOpnd>;
class COPY_U_W_DESC : MSA_COPY_DESC_BASE<"copy_u.w", vextract_zext_i32, v4i32,
GPR32Opnd, MSA128WOpnd>;
uimm2_ptr, immZExt2Ptr, GPR32Opnd,
MSA128WOpnd>;

class COPY_FW_PSEUDO_DESC : MSA_COPY_PSEUDO_BASE<vector_extract, v4f32, FGR32,
class COPY_FW_PSEUDO_DESC : MSA_COPY_PSEUDO_BASE<vector_extract, v4f32,
uimm2_ptr, immZExt2Ptr, FGR32,
MSA128W>;
class COPY_FD_PSEUDO_DESC : MSA_COPY_PSEUDO_BASE<vector_extract, v2f64, FGR64,
class COPY_FD_PSEUDO_DESC : MSA_COPY_PSEUDO_BASE<vector_extract, v2f64,
uimm1_ptr, immZExt1Ptr, FGR64,
MSA128D>;

class CTCMSA_DESC {
Expand Down Expand Up @@ -2249,14 +2250,14 @@ class ILVR_H_DESC : MSA_3R_DESC_BASE<"ilvr.h", MipsILVR, MSA128HOpnd>;
class ILVR_W_DESC : MSA_3R_DESC_BASE<"ilvr.w", MipsILVR, MSA128WOpnd>;
class ILVR_D_DESC : MSA_3R_DESC_BASE<"ilvr.d", MipsILVR, MSA128DOpnd>;

class INSERT_B_DESC : MSA_INSERT_DESC_BASE<"insert.b", vinsert_v16i8,
MSA128BOpnd, GPR32Opnd>;
class INSERT_H_DESC : MSA_INSERT_DESC_BASE<"insert.h", vinsert_v8i16,
MSA128HOpnd, GPR32Opnd>;
class INSERT_W_DESC : MSA_INSERT_DESC_BASE<"insert.w", vinsert_v4i32,
MSA128WOpnd, GPR32Opnd>;
class INSERT_D_DESC : MSA_INSERT_DESC_BASE<"insert.d", vinsert_v2i64,
MSA128DOpnd, GPR64Opnd>;
class INSERT_B_DESC : MSA_INSERT_DESC_BASE<"insert.b", vinsert_v16i8, uimm4,
immZExt4Ptr, MSA128BOpnd, GPR32Opnd>;
class INSERT_H_DESC : MSA_INSERT_DESC_BASE<"insert.h", vinsert_v8i16, uimm3,
immZExt3Ptr, MSA128HOpnd, GPR32Opnd>;
class INSERT_W_DESC : MSA_INSERT_DESC_BASE<"insert.w", vinsert_v4i32, uimm2,
immZExt2Ptr, MSA128WOpnd, GPR32Opnd>;
class INSERT_D_DESC : MSA_INSERT_DESC_BASE<"insert.d", vinsert_v2i64, uimm1,
immZExt1Ptr, MSA128DOpnd, GPR64Opnd>;

class INSERT_B_VIDX_PSEUDO_DESC :
MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v16i8, MSA128BOpnd, GPR32Opnd, GPR32Opnd>;
Expand All @@ -2268,8 +2269,10 @@ class INSERT_D_VIDX_PSEUDO_DESC :
MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2i64, MSA128DOpnd, GPR64Opnd, GPR32Opnd>;

class INSERT_FW_PSEUDO_DESC : MSA_INSERT_PSEUDO_BASE<vector_insert, v4f32,
uimm2, immZExt2Ptr,
MSA128WOpnd, FGR32Opnd>;
class INSERT_FD_PSEUDO_DESC : MSA_INSERT_PSEUDO_BASE<vector_insert, v2f64,
uimm1, immZExt1Ptr,
MSA128DOpnd, FGR64Opnd>;

class INSERT_FW_VIDX_PSEUDO_DESC :
Expand Down
22 changes: 22 additions & 0 deletions llvm/test/MC/Mips/msa/invalid.s
View file
Expand Up @@ -5,6 +5,28 @@
# RUN: FileCheck %s < %t1

.set noat
copy_s.b $2, $w9[-1] # CHECK: :[[@LINE]]:22: error: expected 4-bit unsigned immediate
copy_s.b $2, $w9[16] # CHECK: :[[@LINE]]:22: error: expected 4-bit unsigned immediate
copy_s.h $2, $w9[-1] # CHECK: :[[@LINE]]:22: error: expected 3-bit unsigned immediate
copy_s.h $2, $w9[8] # CHECK: :[[@LINE]]:22: error: expected 3-bit unsigned immediate
copy_s.w $2, $w9[-1] # CHECK: :[[@LINE]]:22: error: expected 2-bit unsigned immediate
copy_s.w $2, $w9[4] # CHECK: :[[@LINE]]:22: error: expected 2-bit unsigned immediate
copy_s.d $2, $w9[-1] # CHECK: :[[@LINE]]:22: error: expected 1-bit unsigned immediate
copy_s.d $2, $w9[2] # CHECK: :[[@LINE]]:22: error: expected 1-bit unsigned immediate
copy_u.b $2, $w9[-1] # CHECK: :[[@LINE]]:22: error: expected 4-bit unsigned immediate
copy_u.b $2, $w9[16] # CHECK: :[[@LINE]]:22: error: expected 4-bit unsigned immediate
copy_u.h $2, $w9[-1] # CHECK: :[[@LINE]]:22: error: expected 3-bit unsigned immediate
copy_u.h $2, $w9[8] # CHECK: :[[@LINE]]:22: error: expected 3-bit unsigned immediate
copy_u.w $2, $w9[-1] # CHECK: :[[@LINE]]:22: error: expected 2-bit unsigned immediate
copy_u.w $2, $w9[4] # CHECK: :[[@LINE]]:22: error: expected 2-bit unsigned immediate
insert.b $w9[-1], $2 # CHECK: :[[@LINE]]:18: error: expected 4-bit unsigned immediate
insert.b $w9[16], $2 # CHECK: :[[@LINE]]:18: error: expected 4-bit unsigned immediate
insert.h $w9[-1], $2 # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate
insert.h $w9[8], $2 # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate
insert.w $w9[-1], $2 # CHECK: :[[@LINE]]:18: error: expected 2-bit unsigned immediate
insert.w $w9[4], $2 # CHECK: :[[@LINE]]:18: error: expected 2-bit unsigned immediate
insert.d $w9[-1], $2 # CHECK: :[[@LINE]]:18: error: expected 1-bit unsigned immediate
insert.d $w9[2], $2 # CHECK: :[[@LINE]]:18: error: expected 1-bit unsigned immediate
insve.b $w25[-1], $w9[0] # CHECK: :[[@LINE]]:18: error: expected 4-bit unsigned immediate
insve.b $w25[16], $w9[0] # CHECK: :[[@LINE]]:18: error: expected 4-bit unsigned immediate
insve.h $w24[-1], $w2[0] # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate
Expand Down

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