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[GlobalISel] Enable CSE in the IRTranslator & legalizer for -O0 with …
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…constants only.

Other opcodes shouldn't be CSE'd until we can be sure debug info quality won't
be degraded.

This change also improves the IRTranslator so that in most places, but not all,
it creates constants using the MIRBuilder directly instead of first creating a
new destination vreg and then creating a constant. By doing this, the
buildConstant() method can just return the vreg of an existing G_CONSTANT
instead of having to create a COPY from it.

I measured a 0.2% improvement in compile time and a 0.9% improvement in code
size at -O0 ARM64.

Compile time:
Program                                        base   cse    diff
test-suite...ark/tramp3d-v4/tramp3d-v4.test     9.04   9.12  0.8%
test-suite...Mark/mafft/pairlocalalign.test     2.68   2.66 -0.7%
test-suite...-typeset/consumer-typeset.test     5.53   5.51 -0.4%
test-suite :: CTMark/lencod/lencod.test         5.30   5.28 -0.3%
test-suite :: CTMark/Bullet/bullet.test        25.82  25.76 -0.2%
test-suite...:: CTMark/ClamAV/clamscan.test     6.92   6.90 -0.2%
test-suite...TMark/7zip/7zip-benchmark.test    34.24  34.17 -0.2%
test-suite :: CTMark/SPASS/SPASS.test           6.25   6.24 -0.1%
test-suite...:: CTMark/sqlite3/sqlite3.test     1.66   1.66 -0.1%
test-suite :: CTMark/kimwitu++/kc.test         13.61  13.60 -0.0%
Geomean difference                                          -0.2%

Code size:
Program                                        base     cse      diff
test-suite...-typeset/consumer-typeset.test    1315632  1266480 -3.7%
test-suite...:: CTMark/ClamAV/clamscan.test    1313892  1297508 -1.2%
test-suite :: CTMark/lencod/lencod.test        1439504  1423112 -1.1%
test-suite...TMark/7zip/7zip-benchmark.test    2936980  2904172 -1.1%
test-suite :: CTMark/Bullet/bullet.test        3478276  3445460 -0.9%
test-suite...ark/tramp3d-v4/tramp3d-v4.test    8082868  8033492 -0.6%
test-suite :: CTMark/kimwitu++/kc.test         3870380  3853972 -0.4%
test-suite :: CTMark/SPASS/SPASS.test          1434904  1434896 -0.0%
test-suite...Mark/mafft/pairlocalalign.test    764528   764528   0.0%
test-suite...:: CTMark/sqlite3/sqlite3.test    782092   782092   0.0%
Geomean difference                                              -0.9%

Differential Revision: https://reviews.llvm.org/D60580

llvm-svn: 358369
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@aemerson
aemerson committed Apr 15, 2019
1 parent d189680 commit 946b124
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Showing 52 changed files with 697 additions and 1,016 deletions.
2 changes: 1 addition & 1 deletion llvm/lib/CodeGen/GlobalISel/CSEInfo.cpp
View file
Expand Up @@ -65,7 +65,7 @@ std::unique_ptr<CSEConfigBase>
llvm::getStandardCSEConfigForOpt(CodeGenOpt::Level Level) {
std::unique_ptr<CSEConfigBase> Config;
if (Level == CodeGenOpt::None)
Config = make_unique<CSEConfigBase>();
Config = make_unique<CSEConfigConstantOnly>();
else
Config = make_unique<CSEConfigFull>();
return Config;
Expand Down
18 changes: 9 additions & 9 deletions llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
View file
Expand Up @@ -645,9 +645,9 @@ bool IRTranslator::translateGetElementPtr(const User &U,

if (Offset != 0) {
unsigned NewBaseReg = MRI->createGenericVirtualRegister(PtrTy);
unsigned OffsetReg =
getOrCreateVReg(*ConstantInt::get(OffsetIRTy, Offset));
MIRBuilder.buildGEP(NewBaseReg, BaseReg, OffsetReg);
LLT OffsetTy = getLLTForType(*OffsetIRTy, *DL);
auto OffsetMIB = MIRBuilder.buildConstant({OffsetTy}, Offset);
MIRBuilder.buildGEP(NewBaseReg, BaseReg, OffsetMIB.getReg(0));

BaseReg = NewBaseReg;
Offset = 0;
Expand All @@ -664,11 +664,10 @@ bool IRTranslator::translateGetElementPtr(const User &U,
// Avoid doing it for ElementSize of 1.
unsigned GepOffsetReg;
if (ElementSize != 1) {
unsigned ElementSizeReg =
getOrCreateVReg(*ConstantInt::get(OffsetIRTy, ElementSize));

GepOffsetReg = MRI->createGenericVirtualRegister(OffsetTy);
MIRBuilder.buildMul(GepOffsetReg, ElementSizeReg, IdxReg);
auto ElementSizeMIB = MIRBuilder.buildConstant(
getLLTForType(*OffsetIRTy, *DL), ElementSize);
MIRBuilder.buildMul(GepOffsetReg, ElementSizeMIB.getReg(0), IdxReg);
} else
GepOffsetReg = IdxReg;

Expand All @@ -679,8 +678,9 @@ bool IRTranslator::translateGetElementPtr(const User &U,
}

if (Offset != 0) {
unsigned OffsetReg = getOrCreateVReg(*ConstantInt::get(OffsetIRTy, Offset));
MIRBuilder.buildGEP(getOrCreateVReg(U), BaseReg, OffsetReg);
auto OffsetMIB =
MIRBuilder.buildConstant(getLLTForType(*OffsetIRTy, *DL), Offset);
MIRBuilder.buildGEP(getOrCreateVReg(U), BaseReg, OffsetMIB.getReg(0));
return true;
}

Expand Down
1 change: 1 addition & 0 deletions llvm/lib/CodeGen/GlobalISel/Legalizer.cpp
View file
Expand Up @@ -27,6 +27,7 @@
#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/Support/Debug.h"
#include "llvm/Target/TargetMachine.h"

#include <iterator>

Expand Down
6 changes: 2 additions & 4 deletions llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
View file
Expand Up @@ -215,10 +215,8 @@ MachineIRBuilder::materializeGEP(unsigned &Res, unsigned Op0,
}

Res = getMRI()->createGenericVirtualRegister(getMRI()->getType(Op0));
unsigned TmpReg = getMRI()->createGenericVirtualRegister(ValueTy);

buildConstant(TmpReg, Value);
return buildGEP(Res, Op0, TmpReg);
auto Cst = buildConstant(ValueTy, Value);
return buildGEP(Res, Op0, Cst.getReg(0));
}

MachineInstrBuilder MachineIRBuilder::buildPtrMask(unsigned Res, unsigned Op0,
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/CodeGen/TargetPassConfig.cpp
View file
Expand Up @@ -1226,7 +1226,7 @@ bool TargetPassConfig::reportDiagnosticWhenGlobalISelFallback() const {
}

bool TargetPassConfig::isGISelCSEEnabled() const {
return getOptLevel() != CodeGenOpt::Level::None;
return true;
}

std::unique_ptr<CSEConfigBase> TargetPassConfig::getCSEConfig() const {
Expand Down
5 changes: 2 additions & 3 deletions llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp
View file
Expand Up @@ -648,11 +648,10 @@ bool AArch64LegalizerInfo::legalizeVaArg(MachineInstr &MI,
*MF.getMachineMemOperand(MachinePointerInfo(), MachineMemOperand::MOLoad,
ValSize, std::max(Align, PtrSize)));

unsigned SizeReg = MRI.createGenericVirtualRegister(IntPtrTy);
MIRBuilder.buildConstant(SizeReg, alignTo(ValSize, PtrSize));
auto Size = MIRBuilder.buildConstant(IntPtrTy, alignTo(ValSize, PtrSize));

unsigned NewList = MRI.createGenericVirtualRegister(PtrTy);
MIRBuilder.buildGEP(NewList, DstPtr, SizeReg);
MIRBuilder.buildGEP(NewList, DstPtr, Size.getReg(0));

MIRBuilder.buildStore(
NewList, ListPtr,
Expand Down
28 changes: 12 additions & 16 deletions llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
View file
Expand Up @@ -698,7 +698,6 @@ unsigned AMDGPULegalizerInfo::getSegmentAperture(
Offset << AMDGPU::Hwreg::OFFSET_SHIFT_ |
WidthM1 << AMDGPU::Hwreg::WIDTH_M1_SHIFT_;

unsigned ShiftAmt = MRI.createGenericVirtualRegister(S32);
unsigned ApertureReg = MRI.createGenericVirtualRegister(S32);
unsigned GetReg = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);

Expand All @@ -707,11 +706,11 @@ unsigned AMDGPULegalizerInfo::getSegmentAperture(
.addImm(Encoding);
MRI.setType(GetReg, S32);

MIRBuilder.buildConstant(ShiftAmt, WidthM1 + 1);
auto ShiftAmt = MIRBuilder.buildConstant(S32, WidthM1 + 1);
MIRBuilder.buildInstr(TargetOpcode::G_SHL)
.addDef(ApertureReg)
.addUse(GetReg)
.addUse(ShiftAmt);
.addUse(ShiftAmt.getReg(0));

return ApertureReg;
}
Expand Down Expand Up @@ -781,20 +780,17 @@ bool AMDGPULegalizerInfo::legalizeAddrSpaceCast(
DestAS == AMDGPUAS::PRIVATE_ADDRESS);
unsigned NullVal = TM.getNullPointerValue(DestAS);

unsigned SegmentNullReg = MRI.createGenericVirtualRegister(DstTy);
unsigned FlatNullReg = MRI.createGenericVirtualRegister(SrcTy);

MIRBuilder.buildConstant(SegmentNullReg, NullVal);
MIRBuilder.buildConstant(FlatNullReg, 0);
auto SegmentNull = MIRBuilder.buildConstant(DstTy, NullVal);
auto FlatNull = MIRBuilder.buildConstant(SrcTy, 0);

unsigned PtrLo32 = MRI.createGenericVirtualRegister(DstTy);

// Extract low 32-bits of the pointer.
MIRBuilder.buildExtract(PtrLo32, Src, 0);

unsigned CmpRes = MRI.createGenericVirtualRegister(LLT::scalar(1));
MIRBuilder.buildICmp(CmpInst::ICMP_NE, CmpRes, Src, FlatNullReg);
MIRBuilder.buildSelect(Dst, CmpRes, PtrLo32, SegmentNullReg);
MIRBuilder.buildICmp(CmpInst::ICMP_NE, CmpRes, Src, FlatNull.getReg(0));
MIRBuilder.buildSelect(Dst, CmpRes, PtrLo32, SegmentNull.getReg(0));

MI.eraseFromParent();
return true;
Expand All @@ -803,15 +799,15 @@ bool AMDGPULegalizerInfo::legalizeAddrSpaceCast(
assert(SrcAS == AMDGPUAS::LOCAL_ADDRESS ||
SrcAS == AMDGPUAS::PRIVATE_ADDRESS);

unsigned FlatNullReg = MRI.createGenericVirtualRegister(DstTy);
unsigned SegmentNullReg = MRI.createGenericVirtualRegister(SrcTy);
MIRBuilder.buildConstant(SegmentNullReg, TM.getNullPointerValue(SrcAS));
MIRBuilder.buildConstant(FlatNullReg, TM.getNullPointerValue(DestAS));
auto SegmentNull =
MIRBuilder.buildConstant(SrcTy, TM.getNullPointerValue(SrcAS));
auto FlatNull =
MIRBuilder.buildConstant(DstTy, TM.getNullPointerValue(DestAS));

unsigned ApertureReg = getSegmentAperture(DestAS, MRI, MIRBuilder);

unsigned CmpRes = MRI.createGenericVirtualRegister(LLT::scalar(1));
MIRBuilder.buildICmp(CmpInst::ICMP_NE, CmpRes, Src, SegmentNullReg);
MIRBuilder.buildICmp(CmpInst::ICMP_NE, CmpRes, Src, SegmentNull.getReg(0));

unsigned BuildPtr = MRI.createGenericVirtualRegister(DstTy);

Expand All @@ -824,7 +820,7 @@ bool AMDGPULegalizerInfo::legalizeAddrSpaceCast(
// TODO: Should we allow mismatched types but matching sizes in merges to
// avoid the ptrtoint?
MIRBuilder.buildMerge(BuildPtr, {SrcAsInt, ApertureReg});
MIRBuilder.buildSelect(Dst, CmpRes, BuildPtr, FlatNullReg);
MIRBuilder.buildSelect(Dst, CmpRes, BuildPtr, FlatNull.getReg(0));

MI.eraseFromParent();
return true;
Expand Down
29 changes: 10 additions & 19 deletions llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
View file
Expand Up @@ -586,7 +586,7 @@ next:
; CHECK-LABEL: name: constant_int_start
; CHECK: [[TWO:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
; CHECK: [[ANSWER:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
; CHECK: [[RES:%[0-9]+]]:_(s32) = G_ADD [[TWO]], [[ANSWER]]
; CHECK: [[RES:%[0-9]+]]:_(s32) = G_CONSTANT i32 44
define i32 @constant_int_start() {
%res = add i32 2, 42
ret i32 %res
Expand Down Expand Up @@ -727,8 +727,7 @@ define i8* @test_constant_null() {
; CHECK: [[GEP1:%[0-9]+]]:_(p0) = G_GEP [[ADDR]], [[CST1]](s64)
; CHECK: [[VAL2:%[0-9]+]]:_(s32) = G_LOAD [[GEP1]](p0) :: (load 4 from %ir.addr + 4)
; CHECK: G_STORE [[VAL1]](s8), [[ADDR]](p0) :: (store 1 into %ir.addr, align 4)
; CHECK: [[CST2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; CHECK: [[GEP2:%[0-9]+]]:_(p0) = G_GEP [[ADDR]], [[CST2]](s64)
; CHECK: [[GEP2:%[0-9]+]]:_(p0) = G_GEP [[ADDR]], [[CST1]](s64)
; CHECK: G_STORE [[VAL2]](s32), [[GEP2]](p0) :: (store 4 into %ir.addr + 4)
define void @test_struct_memops({ i8, i32 }* %addr) {
%val = load { i8, i32 }, { i8, i32 }* %addr
Expand Down Expand Up @@ -965,8 +964,7 @@ define i32 @test_extractvalue(%struct.nested* %addr) {
; CHECK: [[GEP3:%[0-9]+]]:_(p0) = G_GEP %0, [[CST3]](s64)
; CHECK: [[LD4:%[0-9]+]]:_(s32) = G_LOAD [[GEP3]](p0) :: (load 4 from %ir.addr + 12)
; CHECK: G_STORE [[LD2]](s8), %1(p0) :: (store 1 into %ir.addr2, align 4)
; CHECK: [[CST4:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; CHECK: [[GEP4:%[0-9]+]]:_(p0) = G_GEP %1, [[CST4]](s64)
; CHECK: [[GEP4:%[0-9]+]]:_(p0) = G_GEP %1, [[CST1]](s64)
; CHECK: G_STORE [[LD3]](s32), [[GEP4]](p0) :: (store 4 into %ir.addr2 + 4)
define void @test_extractvalue_agg(%struct.nested* %addr, {i8, i32}* %addr2) {
%struct = load %struct.nested, %struct.nested* %addr
Expand All @@ -989,14 +987,11 @@ define void @test_extractvalue_agg(%struct.nested* %addr, {i8, i32}* %addr2) {
; CHECK: [[GEP3:%[0-9]+]]:_(p0) = G_GEP %0, [[CST3]](s64)
; CHECK: [[LD4:%[0-9]+]]:_(s32) = G_LOAD [[GEP3]](p0) :: (load 4 from %ir.addr + 12)
; CHECK: G_STORE [[LD1]](s8), %0(p0) :: (store 1 into %ir.addr, align 4)
; CHECK: [[CST4:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; CHECK: [[GEP4:%[0-9]+]]:_(p0) = G_GEP %0, [[CST4]](s64)
; CHECK: [[GEP4:%[0-9]+]]:_(p0) = G_GEP %0, [[CST1]](s64)
; CHECK: G_STORE [[LD2]](s8), [[GEP4]](p0) :: (store 1 into %ir.addr + 4, align 4)
; CHECK: [[CST5:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; CHECK: [[GEP5:%[0-9]+]]:_(p0) = G_GEP %0, [[CST5]](s64)
; CHECK: [[GEP5:%[0-9]+]]:_(p0) = G_GEP %0, [[CST2]](s64)
; CHECK: G_STORE %1(s32), [[GEP5]](p0) :: (store 4 into %ir.addr + 8)
; CHECK: [[CST6:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
; CHECK: [[GEP6:%[0-9]+]]:_(p0) = G_GEP %0, [[CST6]](s64)
; CHECK: [[GEP6:%[0-9]+]]:_(p0) = G_GEP %0, [[CST3]](s64)
; CHECK: G_STORE [[LD4]](s32), [[GEP6]](p0) :: (store 4 into %ir.addr + 12)
define void @test_insertvalue(%struct.nested* %addr, i32 %val) {
%struct = load %struct.nested, %struct.nested* %addr
Expand Down Expand Up @@ -1031,8 +1026,7 @@ define [1 x i8*] @test_trivial_insert_ptr([1 x i8*] %s, i8* %val) {
; CHECK: [[GEP1:%[0-9]+]]:_(p0) = G_GEP %1, [[CST1]](s64)
; CHECK: [[LD2:%[0-9]+]]:_(s32) = G_LOAD [[GEP1]](p0) :: (load 4 from %ir.addr2 + 4)
; CHECK: [[LD3:%[0-9]+]]:_(s8) = G_LOAD %0(p0) :: (load 1 from %ir.addr, align 4)
; CHECK: [[CST2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; CHECK: [[GEP2:%[0-9]+]]:_(p0) = G_GEP %0, [[CST2]](s64)
; CHECK: [[GEP2:%[0-9]+]]:_(p0) = G_GEP %0, [[CST1]](s64)
; CHECK: [[LD4:%[0-9]+]]:_(s8) = G_LOAD [[GEP2]](p0) :: (load 1 from %ir.addr + 4, align 4)
; CHECK: [[CST3:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; CHECK: [[GEP3:%[0-9]+]]:_(p0) = G_GEP %0, [[CST3]](s64)
Expand All @@ -1041,14 +1035,11 @@ define [1 x i8*] @test_trivial_insert_ptr([1 x i8*] %s, i8* %val) {
; CHECK: [[GEP4:%[0-9]+]]:_(p0) = G_GEP %0, [[CST4]](s64)
; CHECK: [[LD6:%[0-9]+]]:_(s32) = G_LOAD [[GEP4]](p0) :: (load 4 from %ir.addr + 12)
; CHECK: G_STORE [[LD3]](s8), %0(p0) :: (store 1 into %ir.addr, align 4)
; CHECK: [[CST5:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; CHECK: [[GEP5:%[0-9]+]]:_(p0) = G_GEP %0, [[CST5]](s64)
; CHECK: [[GEP5:%[0-9]+]]:_(p0) = G_GEP %0, [[CST1]](s64)
; CHECK: G_STORE [[LD1]](s8), [[GEP5]](p0) :: (store 1 into %ir.addr + 4, align 4)
; CHECK: [[CST6:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; CHECK: [[GEP6:%[0-9]+]]:_(p0) = G_GEP %0, [[CST6]](s64)
; CHECK: [[GEP6:%[0-9]+]]:_(p0) = G_GEP %0, [[CST3]](s64)
; CHECK: G_STORE [[LD2]](s32), [[GEP6]](p0) :: (store 4 into %ir.addr + 8)
; CHECK: [[CST7:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
; CHECK: [[GEP7:%[0-9]+]]:_(p0) = G_GEP %0, [[CST7]](s64)
; CHECK: [[GEP7:%[0-9]+]]:_(p0) = G_GEP %0, [[CST4]](s64)
; CHECK: G_STORE [[LD6]](s32), [[GEP7]](p0) :: (store 4 into %ir.addr + 12)
define void @test_insertvalue_agg(%struct.nested* %addr, {i8, i32}* %addr2) {
%smallstruct = load {i8, i32}, {i8, i32}* %addr2
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AArch64/GlobalISel/call-translator-ios.ll
View file
Expand Up @@ -71,7 +71,7 @@ define void @take_128bit_struct([2 x i64]* %ptr, [2 x i64] %in) {
; CHECK: G_STORE [[EXT1]](s64), [[ADDR]](p0) :: (store 8 into stack, align 1)

; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[OFF:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; CHECK: [[OFF:%[0-9]+]]:_(s64) = COPY [[CST]]
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[OFF]]
; CHECK: G_STORE [[EXT2]](s64), [[ADDR]](p0) :: (store 8 into stack + 8, align 1)
define void @test_split_struct([2 x i64]* %ptr) {
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AArch64/GlobalISel/call-translator.ll
View file
Expand Up @@ -282,7 +282,7 @@ define void @take_128bit_struct([2 x i64]* %ptr, [2 x i64] %in) {
; CHECK: [[GEP2:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[CST2]](s64)
; CHECK: G_STORE [[EXTLO]](s64), [[GEP2]](p0) :: (store 8 into stack, align 1)
; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[CST3:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; CHECK: [[CST3:%[0-9]+]]:_(s64) = COPY [[CST]]
; CHECK: [[GEP3:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[CST3]](s64)
; CHECK: G_STORE [[EXTHI]](s64), [[GEP3]](p0) :: (store 8 into stack + 8, align 1)
define void @test_split_struct([2 x i64]* %ptr) {
Expand Down
3 changes: 1 addition & 2 deletions llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir
View file
Expand Up @@ -13,9 +13,8 @@ body: |
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C1]]
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C]]
; CHECK: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[AND]](s32), [[AND1]]
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32)
; CHECK: $w0 = COPY [[COPY3]](s32)
Expand Down
8 changes: 3 additions & 5 deletions llvm/test/CodeGen/AArch64/GlobalISel/legalize-div.mir
View file
Expand Up @@ -11,19 +11,17 @@ body: |
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C]](s32)
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[TRUNC1]], [[C1]](s32)
; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C1]](s32)
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[TRUNC1]], [[C]](s32)
; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32)
; CHECK: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[ASHR]], [[ASHR1]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SDIV]](s32)
; CHECK: $w0 = COPY [[COPY2]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC2]], [[C2]]
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC3]], [[C3]]
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC3]], [[C2]]
; CHECK: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[AND]], [[AND1]]
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UDIV]](s32)
; CHECK: $w0 = COPY [[COPY3]](s32)
Expand Down
5 changes: 1 addition & 4 deletions llvm/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir
View file
Expand Up @@ -49,9 +49,8 @@ body: |
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[TRUNC9]], [[C5]]
; CHECK: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C5]]
; CHECK: $w0 = COPY [[ASHR2]](s32)
; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[TRUNC10:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[TRUNC10]], [[C6]]
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[TRUNC10]], [[C4]]
; CHECK: $w0 = COPY [[AND3]](s32)
; CHECK: [[TRUNC11:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: $w0 = COPY [[TRUNC11]](s32)
Expand All @@ -61,8 +60,6 @@ body: |
; CHECK: $x0 = COPY [[FPEXT]](s64)
; CHECK: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: $w0 = COPY [[C7]](s32)
; CHECK: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: $w0 = COPY [[C8]](s32)
; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; CHECK: $w0 = COPY [[DEF]](s32)
%0:_(s64) = COPY $x0
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3 changes: 1 addition & 2 deletions llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-s128-unaligned.mir
View file
Expand Up @@ -18,8 +18,7 @@ body: |
; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY]], [[C]](s64)
; CHECK: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[GEP]](p0) :: (load 8, align 4)
; CHECK: G_STORE [[LOAD]](s64), [[COPY1]](p0) :: (store 8, align 4)
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; CHECK: [[GEP1:%[0-9]+]]:_(p0) = G_GEP [[COPY1]], [[C1]](s64)
; CHECK: [[GEP1:%[0-9]+]]:_(p0) = G_GEP [[COPY1]], [[C]](s64)
; CHECK: G_STORE [[LOAD1]](s64), [[GEP1]](p0) :: (store 8, align 4)
; CHECK: RET_ReallyLR
%0:_(p0) = COPY $x0
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3 changes: 1 addition & 2 deletions llvm/test/CodeGen/AArch64/GlobalISel/legalize-merge-values.mir
View file
Expand Up @@ -15,9 +15,8 @@ body: |
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C3]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[AND]](s32)
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C4]]
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C3]]
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SHL]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[COPY1]]
; CHECK: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[OR]](s32)
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3 changes: 1 addition & 2 deletions llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir
View file
Expand Up @@ -451,9 +451,8 @@ body: |
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI]](s16)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C4]]
; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI1]](s16)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C5]]
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C4]]
; CHECK: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]]
; CHECK: $w0 = COPY [[ADD2]](s32)
; CHECK: RET_ReallyLR implicit $w0
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5 changes: 2 additions & 3 deletions llvm/test/CodeGen/AArch64/GlobalISel/legalize-rem.mir
View file
Expand Up @@ -49,10 +49,9 @@ body: |
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C]]
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[TRUNC1]], [[C1]]
; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C1]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[TRUNC1]], [[C]]
; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]]
; CHECK: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[ASHR]], [[ASHR1]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SDIV]](s32)
; CHECK: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
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