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[MachinePipeliner] Fix order for nodes with Anti dependence in same c…
…ycle Summary: Problem exposed in PowerPC functional testing. We did not consider Anti dependence for nodes in same cycle, so we may end up generating bad machine code. eg: the reduced test won't verify. *** Bad machine code: Using an undefined physical register *** - function: lame_encode_buffer_interleaved - basic block: %bb.4 (0x4bde4e12928) - instruction: %29:gprc = ADDZE %27:gprc, implicit-def dead $carry, implicit $carry - operand 3: implicit $carry Reviewers: bcahoon, kparzysz, hfinkel Subscribers: MaskRay, wuzish, nemanjai, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64192 llvm-svn: 365859
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Jinsong Ji
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Jul 12, 2019
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Original file line number | Diff line number | Diff line change |
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py | ||
; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs\ | ||
; RUN: -mcpu=pwr9 --ppc-enable-pipeliner | FileCheck %s | ||
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define void @lame_encode_buffer_interleaved() local_unnamed_addr { | ||
; CHECK-LABEL: lame_encode_buffer_interleaved: | ||
; CHECK: # %bb.0: | ||
; CHECK-NEXT: lhz 3, 0(0) | ||
; CHECK-NEXT: li 5, 1 | ||
; CHECK-NEXT: sldi 5, 5, 62 | ||
; CHECK-NEXT: lhz 4, 0(3) | ||
; CHECK-NEXT: mtctr 5 | ||
; CHECK-NEXT: .p2align 5 | ||
; CHECK-NEXT: .LBB0_1: # | ||
; CHECK-NEXT: extsh 3, 3 | ||
; CHECK-NEXT: extsh 4, 4 | ||
; CHECK-NEXT: srawi 3, 3, 1 | ||
; CHECK-NEXT: addze 3, 3 | ||
; CHECK-NEXT: srawi 4, 4, 1 | ||
; CHECK-NEXT: addze 4, 4 | ||
; CHECK-NEXT: bdnz .LBB0_1 | ||
; CHECK-NEXT: # %bb.2: | ||
; CHECK-NEXT: sth 3, 0(0) | ||
; CHECK-NEXT: sth 4, 0(3) | ||
; CHECK-NEXT: blr | ||
br label %1 | ||
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1: ; preds = %1, %0 | ||
%2 = phi i64 [ 0, %0 ], [ %13, %1 ] | ||
%3 = load i16, i16* null, align 2 | ||
%4 = load i16, i16* undef, align 2 | ||
%5 = sext i16 %3 to i32 | ||
%6 = sext i16 %4 to i32 | ||
%7 = add nsw i32 0, %5 | ||
%8 = add nsw i32 0, %6 | ||
%9 = sdiv i32 %7, 2 | ||
%10 = sdiv i32 %8, 2 | ||
%11 = trunc i32 %9 to i16 | ||
%12 = trunc i32 %10 to i16 | ||
store i16 %11, i16* null, align 2 | ||
store i16 %12, i16* undef, align 2 | ||
%13 = add i64 %2, 4 | ||
%14 = icmp eq i64 %13, 0 | ||
br i1 %14, label %15, label %1 | ||
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15: ; preds = %1 | ||
ret void | ||
} |