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Differential Revision: https://reviews.llvm.org/D65767 llvm-svn: 367972
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24 changes: 24 additions & 0 deletions
24
llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/AsmParser/BUILD.gn
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import("//llvm/utils/TableGen/tablegen.gni") | ||
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tablegen("AMDGPUGenAsmMatcher") { | ||
visibility = [ ":AsmParser" ] | ||
args = [ "-gen-asm-matcher" ] | ||
td_file = "../AMDGPU.td" | ||
} | ||
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static_library("AsmParser") { | ||
output_name = "LLVMAMDGPUAsmParser" | ||
deps = [ | ||
":AMDGPUGenAsmMatcher", | ||
"//llvm/lib/MC", | ||
"//llvm/lib/MC/MCParser", | ||
"//llvm/lib/Support", | ||
"//llvm/lib/Target/AMDGPU/MCTargetDesc", | ||
"//llvm/lib/Target/AMDGPU/TargetInfo", | ||
"//llvm/lib/Target/AMDGPU/Utils", | ||
] | ||
include_dirs = [ ".." ] | ||
sources = [ | ||
"AMDGPUAsmParser.cpp", | ||
] | ||
} |
197 changes: 197 additions & 0 deletions
197
llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn
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import("//llvm/utils/TableGen/tablegen.gni") | ||
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tablegen("AMDGPUGenAsmMatcher") { | ||
visibility = [ ":LLVMAMDGPUCodeGen" ] | ||
args = [ "-gen-asm-matcher" ] | ||
td_file = "AMDGPU.td" | ||
} | ||
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tablegen("AMDGPUGenCallingConv") { | ||
visibility = [ ":LLVMAMDGPUCodeGen" ] | ||
args = [ "-gen-callingconv" ] | ||
td_file = "AMDGPU.td" | ||
} | ||
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tablegen("AMDGPUGenDAGISel") { | ||
visibility = [ ":LLVMAMDGPUCodeGen" ] | ||
args = [ "-gen-dag-isel" ] | ||
td_file = "AMDGPU.td" | ||
} | ||
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tablegen("AMDGPUGenGlobalISel") { | ||
visibility = [ ":LLVMAMDGPUCodeGen" ] | ||
args = [ "-gen-global-isel" ] | ||
td_file = "AMDGPUGISel.td" | ||
} | ||
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tablegen("AMDGPUGenMCPseudoLowering") { | ||
visibility = [ ":LLVMAMDGPUCodeGen" ] | ||
args = [ "-gen-pseudo-lowering" ] | ||
td_file = "AMDGPU.td" | ||
} | ||
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tablegen("AMDGPUGenRegisterBank") { | ||
visibility = [ ":LLVMAMDGPUCodeGen" ] | ||
args = [ "-gen-register-bank" ] | ||
td_file = "AMDGPU.td" | ||
} | ||
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tablegen("R600GenCallingConv") { | ||
visibility = [ ":LLVMAMDGPUCodeGen" ] | ||
args = [ "-gen-callingconv" ] | ||
td_file = "R600.td" | ||
} | ||
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tablegen("R600GenDAGISel") { | ||
visibility = [ ":LLVMAMDGPUCodeGen" ] | ||
args = [ "-gen-dag-isel" ] | ||
td_file = "R600.td" | ||
} | ||
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tablegen("R600GenDFAPacketizer") { | ||
visibility = [ ":LLVMAMDGPUCodeGen" ] | ||
args = [ "-gen-dfa-packetizer" ] | ||
td_file = "R600.td" | ||
} | ||
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static_library("LLVMAMDGPUCodeGen") { | ||
deps = [ | ||
":AMDGPUGenAsmMatcher", | ||
":AMDGPUGenCallingConv", | ||
":AMDGPUGenDAGISel", | ||
":AMDGPUGenGlobalISel", | ||
":AMDGPUGenMCPseudoLowering", | ||
":AMDGPUGenRegisterBank", | ||
":R600GenCallingConv", | ||
":R600GenDAGISel", | ||
":R600GenDFAPacketizer", | ||
"MCTargetDesc", | ||
"TargetInfo", | ||
"Utils", | ||
"//llvm/lib/Analysis", | ||
"//llvm/lib/CodeGen", | ||
"//llvm/lib/CodeGen/AsmPrinter", | ||
"//llvm/lib/CodeGen/GlobalISel", | ||
"//llvm/lib/CodeGen/MIRParser", | ||
"//llvm/lib/CodeGen/SelectionDAG", | ||
"//llvm/lib/IR", | ||
"//llvm/lib/MC", | ||
"//llvm/lib/Support", | ||
"//llvm/lib/Target", | ||
"//llvm/lib/Transforms/IPO", | ||
"//llvm/lib/Transforms/Scalar", | ||
"//llvm/lib/Transforms/Utils", | ||
] | ||
include_dirs = [ "." ] | ||
sources = [ | ||
"AMDGPUAliasAnalysis.cpp", | ||
"AMDGPUAlwaysInlinePass.cpp", | ||
"AMDGPUAnnotateKernelFeatures.cpp", | ||
"AMDGPUAnnotateUniformValues.cpp", | ||
"AMDGPUArgumentUsageInfo.cpp", | ||
"AMDGPUAsmPrinter.cpp", | ||
"AMDGPUAtomicOptimizer.cpp", | ||
"AMDGPUCallLowering.cpp", | ||
"AMDGPUCodeGenPrepare.cpp", | ||
"AMDGPUFixFunctionBitcasts.cpp", | ||
"AMDGPUFrameLowering.cpp", | ||
"AMDGPUHSAMetadataStreamer.cpp", | ||
"AMDGPUISelDAGToDAG.cpp", | ||
"AMDGPUISelLowering.cpp", | ||
"AMDGPUInline.cpp", | ||
"AMDGPUInstrInfo.cpp", | ||
"AMDGPUInstructionSelector.cpp", | ||
"AMDGPULegalizerInfo.cpp", | ||
"AMDGPULibCalls.cpp", | ||
"AMDGPULibFunc.cpp", | ||
"AMDGPULowerIntrinsics.cpp", | ||
"AMDGPULowerKernelArguments.cpp", | ||
"AMDGPULowerKernelAttributes.cpp", | ||
"AMDGPUMCInstLower.cpp", | ||
"AMDGPUMachineCFGStructurizer.cpp", | ||
"AMDGPUMachineFunction.cpp", | ||
"AMDGPUMachineModuleInfo.cpp", | ||
"AMDGPUMacroFusion.cpp", | ||
"AMDGPUOpenCLEnqueuedBlockLowering.cpp", | ||
"AMDGPUPerfHintAnalysis.cpp", | ||
"AMDGPUPromoteAlloca.cpp", | ||
"AMDGPUPropagateAttributes.cpp", | ||
"AMDGPURegisterBankInfo.cpp", | ||
"AMDGPURegisterInfo.cpp", | ||
"AMDGPURewriteOutArguments.cpp", | ||
"AMDGPUSubtarget.cpp", | ||
"AMDGPUTargetMachine.cpp", | ||
"AMDGPUTargetObjectFile.cpp", | ||
"AMDGPUTargetTransformInfo.cpp", | ||
"AMDGPUUnifyDivergentExitNodes.cpp", | ||
"AMDGPUUnifyMetadata.cpp", | ||
"AMDILCFGStructurizer.cpp", | ||
"GCNDPPCombine.cpp", | ||
"GCNHazardRecognizer.cpp", | ||
"GCNILPSched.cpp", | ||
"GCNIterativeScheduler.cpp", | ||
"GCNMinRegStrategy.cpp", | ||
"GCNNSAReassign.cpp", | ||
"GCNRegBankReassign.cpp", | ||
"GCNRegPressure.cpp", | ||
"GCNSchedStrategy.cpp", | ||
"R600AsmPrinter.cpp", | ||
"R600ClauseMergePass.cpp", | ||
"R600ControlFlowFinalizer.cpp", | ||
"R600EmitClauseMarkers.cpp", | ||
"R600ExpandSpecialInstrs.cpp", | ||
"R600FrameLowering.cpp", | ||
"R600ISelLowering.cpp", | ||
"R600InstrInfo.cpp", | ||
"R600MachineFunctionInfo.cpp", | ||
"R600MachineScheduler.cpp", | ||
"R600OpenCLImageTypeLoweringPass.cpp", | ||
"R600OptimizeVectorRegisters.cpp", | ||
"R600Packetizer.cpp", | ||
"R600RegisterInfo.cpp", | ||
"SIAddIMGInit.cpp", | ||
"SIAnnotateControlFlow.cpp", | ||
"SIFixSGPRCopies.cpp", | ||
"SIFixVGPRCopies.cpp", | ||
"SIFixupVectorISel.cpp", | ||
"SIFoldOperands.cpp", | ||
"SIFormMemoryClauses.cpp", | ||
"SIFrameLowering.cpp", | ||
"SIISelLowering.cpp", | ||
"SIInsertSkips.cpp", | ||
"SIInsertWaitcnts.cpp", | ||
"SIInstrInfo.cpp", | ||
"SILoadStoreOptimizer.cpp", | ||
"SILowerControlFlow.cpp", | ||
"SILowerI1Copies.cpp", | ||
"SILowerSGPRSpills.cpp", | ||
"SIMachineFunctionInfo.cpp", | ||
"SIMachineScheduler.cpp", | ||
"SIMemoryLegalizer.cpp", | ||
"SIModeRegister.cpp", | ||
"SIOptimizeExecMasking.cpp", | ||
"SIOptimizeExecMaskingPreRA.cpp", | ||
"SIPeepholeSDWA.cpp", | ||
"SIPreAllocateWWMRegs.cpp", | ||
"SIRegisterInfo.cpp", | ||
"SIShrinkInstructions.cpp", | ||
"SIWholeQuadMode.cpp", | ||
] | ||
} | ||
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# This is a bit different from most build files: Due to this group | ||
# having the directory's name, "//llvm/lib/Target/AMDGPU" will refer to this | ||
# target, which pulls in the code in this directory *and all subdirectories*. | ||
# For most other directories, "//llvm/lib/Foo" only pulls in the code directly | ||
# in "llvm/lib/Foo". The forwarding targets in //llvm/lib/Target expect this | ||
# different behavior. | ||
group("AMDGPU") { | ||
deps = [ | ||
":LLVMAMDGPUCodeGen", | ||
"AsmParser", | ||
"Disassembler", | ||
"MCTargetDesc", | ||
"TargetInfo", | ||
"Utils", | ||
] | ||
} |
24 changes: 24 additions & 0 deletions
24
llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/Disassembler/BUILD.gn
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import("//llvm/utils/TableGen/tablegen.gni") | ||
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tablegen("AMDGPUGenDisassemblerTables") { | ||
visibility = [ ":Disassembler" ] | ||
args = [ "-gen-disassembler" ] | ||
td_file = "../AMDGPU.td" | ||
} | ||
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static_library("Disassembler") { | ||
output_name = "LLVMAMDGPUDisassembler" | ||
deps = [ | ||
":AMDGPUGenDisassemblerTables", | ||
"//llvm/lib/MC", | ||
"//llvm/lib/MC/MCDisassembler", | ||
"//llvm/lib/Support", | ||
"//llvm/lib/Target/AMDGPU/MCTargetDesc", | ||
"//llvm/lib/Target/AMDGPU/TargetInfo", | ||
"//llvm/lib/Target/AMDGPU/Utils", | ||
] | ||
include_dirs = [ ".." ] | ||
sources = [ | ||
"AMDGPUDisassembler.cpp", | ||
] | ||
} |
112 changes: 112 additions & 0 deletions
112
llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/MCTargetDesc/BUILD.gn
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import("//llvm/utils/TableGen/tablegen.gni") | ||
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tablegen("AMDGPUGenAsmWriter") { | ||
visibility = [ ":MCTargetDesc" ] | ||
args = [ "-gen-asm-writer" ] | ||
td_file = "../AMDGPU.td" | ||
} | ||
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tablegen("AMDGPUGenInstrInfo") { | ||
visibility = [ ":tablegen" ] | ||
args = [ "-gen-instr-info" ] | ||
td_file = "../AMDGPU.td" | ||
} | ||
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tablegen("AMDGPUGenMCCodeEmitter") { | ||
visibility = [ ":MCTargetDesc" ] | ||
args = [ "-gen-emitter" ] | ||
td_file = "../AMDGPU.td" | ||
} | ||
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tablegen("AMDGPUGenRegisterInfo") { | ||
visibility = [ ":tablegen" ] | ||
args = [ "-gen-register-info" ] | ||
td_file = "../AMDGPU.td" | ||
} | ||
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tablegen("AMDGPUGenSubtargetInfo") { | ||
visibility = [ ":tablegen" ] | ||
args = [ "-gen-subtarget" ] | ||
td_file = "../AMDGPU.td" | ||
} | ||
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tablegen("R600GenAsmWriter") { | ||
visibility = [ ":MCTargetDesc" ] | ||
args = [ "-gen-asm-writer" ] | ||
td_file = "../R600.td" | ||
} | ||
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tablegen("R600GenInstrInfo") { | ||
visibility = [ ":tablegen" ] | ||
args = [ "-gen-instr-info" ] | ||
td_file = "../R600.td" | ||
} | ||
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tablegen("R600GenMCCodeEmitter") { | ||
visibility = [ ":MCTargetDesc" ] | ||
args = [ "-gen-emitter" ] | ||
td_file = "../R600.td" | ||
} | ||
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tablegen("R600GenRegisterInfo") { | ||
visibility = [ ":tablegen" ] | ||
args = [ "-gen-register-info" ] | ||
td_file = "../R600.td" | ||
} | ||
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tablegen("R600GenSubtargetInfo") { | ||
visibility = [ ":tablegen" ] | ||
args = [ "-gen-subtarget" ] | ||
td_file = "../R600.td" | ||
} | ||
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# This should contain tablegen targets generating .inc files included | ||
# by other targets. .inc files only used by .cpp files in this directory | ||
# should be in deps on the static_library instead. | ||
group("tablegen") { | ||
visibility = [ | ||
":MCTargetDesc", | ||
"../Utils", | ||
] | ||
public_deps = [ | ||
":AMDGPUGenInstrInfo", | ||
":AMDGPUGenRegisterInfo", | ||
":AMDGPUGenSubtargetInfo", | ||
":R600GenInstrInfo", | ||
":R600GenRegisterInfo", | ||
":R600GenSubtargetInfo", | ||
] | ||
} | ||
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static_library("MCTargetDesc") { | ||
output_name = "LLVMAMDGPUDesc" | ||
public_deps = [ | ||
":tablegen", | ||
] | ||
deps = [ | ||
":AMDGPUGenAsmWriter", | ||
":AMDGPUGenMCCodeEmitter", | ||
":R600GenAsmWriter", | ||
":R600GenMCCodeEmitter", | ||
"//llvm/lib/BinaryFormat", | ||
"//llvm/lib/IR", | ||
"//llvm/lib/MC", | ||
"//llvm/lib/Support", | ||
"//llvm/lib/Target/AMDGPU/TargetInfo", | ||
"//llvm/lib/Target/AMDGPU/Utils", | ||
] | ||
include_dirs = [ ".." ] | ||
sources = [ | ||
"AMDGPUAsmBackend.cpp", | ||
"AMDGPUELFObjectWriter.cpp", | ||
"AMDGPUELFStreamer.cpp", | ||
"AMDGPUInstPrinter.cpp", | ||
"AMDGPUMCAsmInfo.cpp", | ||
"AMDGPUMCCodeEmitter.cpp", | ||
"AMDGPUMCTargetDesc.cpp", | ||
"AMDGPUTargetStreamer.cpp", | ||
"R600MCCodeEmitter.cpp", | ||
"R600MCTargetDesc.cpp", | ||
"SIMCCodeEmitter.cpp", | ||
] | ||
} |
10 changes: 10 additions & 0 deletions
10
llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/TargetInfo/BUILD.gn
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static_library("TargetInfo") { | ||
output_name = "LLVMAMDGPUInfo" | ||
deps = [ | ||
"//llvm/lib/Support", | ||
] | ||
include_dirs = [ ".." ] | ||
sources = [ | ||
"AMDGPUTargetInfo.cpp", | ||
] | ||
} |
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