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[AArch64] Fix check lines for arm64-neon-across.ll. NFC
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Commit de0707a updated the check lines, but
due to conflicting assembly not all functions kept their checks. This now
distinguishes between selection-dag and global isel.
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@davemgreen
davemgreen committed Jun 15, 2023
1 parent 1643197 commit 98153b0
Showing 1 changed file with 178 additions and 2 deletions.
180 changes: 178 additions & 2 deletions llvm/test/CodeGen/AArch64/arm64-neon-across.ll
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon | FileCheck %s
; RUN: llc < %s -global-isel=1 -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon | FileCheck %s
; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefixes=CHECK,CHECK-SD
; RUN: llc < %s -global-isel=1 -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefixes=CHECK,CHECK-GI

declare float @llvm.aarch64.neon.fminnmv.f32.v4f32(<4 x float>)

Expand Down Expand Up @@ -195,13 +195,35 @@ entry:
}

define i8 @test_vmaxv_s8(<8 x i8> %a) {
; CHECK-SD-LABEL: test_vmaxv_s8:
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: smaxv b0, v0.8b
; CHECK-SD-NEXT: fmov w0, s0
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: test_vmaxv_s8:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: smaxv b0, v0.8b
; CHECK-GI-NEXT: smov w0, v0.b[0]
; CHECK-GI-NEXT: ret
entry:
%smaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v8i8(<8 x i8> %a)
%0 = trunc i32 %smaxv.i to i8
ret i8 %0
}

define i16 @test_vmaxv_s16(<4 x i16> %a) {
; CHECK-SD-LABEL: test_vmaxv_s16:
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: smaxv h0, v0.4h
; CHECK-SD-NEXT: fmov w0, s0
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: test_vmaxv_s16:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: smaxv h0, v0.4h
; CHECK-GI-NEXT: smov w0, v0.h[0]
; CHECK-GI-NEXT: ret
entry:
%smaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v4i16(<4 x i16> %a)
%0 = trunc i32 %smaxv.i to i16
Expand Down Expand Up @@ -233,13 +255,35 @@ entry:
}

define i8 @test_vmaxvq_s8(<16 x i8> %a) {
; CHECK-SD-LABEL: test_vmaxvq_s8:
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: smaxv b0, v0.16b
; CHECK-SD-NEXT: fmov w0, s0
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: test_vmaxvq_s8:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: smaxv b0, v0.16b
; CHECK-GI-NEXT: smov w0, v0.b[0]
; CHECK-GI-NEXT: ret
entry:
%smaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v16i8(<16 x i8> %a)
%0 = trunc i32 %smaxv.i to i8
ret i8 %0
}

define i16 @test_vmaxvq_s16(<8 x i16> %a) {
; CHECK-SD-LABEL: test_vmaxvq_s16:
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: smaxv h0, v0.8h
; CHECK-SD-NEXT: fmov w0, s0
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: test_vmaxvq_s16:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: smaxv h0, v0.8h
; CHECK-GI-NEXT: smov w0, v0.h[0]
; CHECK-GI-NEXT: ret
entry:
%smaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v8i16(<8 x i16> %a)
%0 = trunc i32 %smaxv.i to i16
Expand Down Expand Up @@ -293,13 +337,35 @@ entry:
}

define i8 @test_vminv_s8(<8 x i8> %a) {
; CHECK-SD-LABEL: test_vminv_s8:
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: sminv b0, v0.8b
; CHECK-SD-NEXT: fmov w0, s0
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: test_vminv_s8:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: sminv b0, v0.8b
; CHECK-GI-NEXT: smov w0, v0.b[0]
; CHECK-GI-NEXT: ret
entry:
%sminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v8i8(<8 x i8> %a)
%0 = trunc i32 %sminv.i to i8
ret i8 %0
}

define i16 @test_vminv_s16(<4 x i16> %a) {
; CHECK-SD-LABEL: test_vminv_s16:
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: sminv h0, v0.4h
; CHECK-SD-NEXT: fmov w0, s0
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: test_vminv_s16:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: sminv h0, v0.4h
; CHECK-GI-NEXT: smov w0, v0.h[0]
; CHECK-GI-NEXT: ret
entry:
%sminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v4i16(<4 x i16> %a)
%0 = trunc i32 %sminv.i to i16
Expand Down Expand Up @@ -331,13 +397,35 @@ entry:
}

define i8 @test_vminvq_s8(<16 x i8> %a) {
; CHECK-SD-LABEL: test_vminvq_s8:
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: sminv b0, v0.16b
; CHECK-SD-NEXT: fmov w0, s0
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: test_vminvq_s8:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: sminv b0, v0.16b
; CHECK-GI-NEXT: smov w0, v0.b[0]
; CHECK-GI-NEXT: ret
entry:
%sminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v16i8(<16 x i8> %a)
%0 = trunc i32 %sminv.i to i8
ret i8 %0
}

define i16 @test_vminvq_s16(<8 x i16> %a) {
; CHECK-SD-LABEL: test_vminvq_s16:
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: sminv h0, v0.8h
; CHECK-SD-NEXT: fmov w0, s0
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: test_vminvq_s16:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: sminv h0, v0.8h
; CHECK-GI-NEXT: smov w0, v0.h[0]
; CHECK-GI-NEXT: ret
entry:
%sminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v8i16(<8 x i16> %a)
%0 = trunc i32 %sminv.i to i16
Expand Down Expand Up @@ -391,41 +479,107 @@ entry:
}

define i8 @test_vaddv_s8(<8 x i8> %a) {
; CHECK-SD-LABEL: test_vaddv_s8:
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: addv b0, v0.8b
; CHECK-SD-NEXT: fmov w0, s0
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: test_vaddv_s8:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: addv b0, v0.8b
; CHECK-GI-NEXT: smov w0, v0.b[0]
; CHECK-GI-NEXT: ret
entry:
%vaddv.i = tail call i32 @llvm.aarch64.neon.saddv.i32.v8i8(<8 x i8> %a)
%0 = trunc i32 %vaddv.i to i8
ret i8 %0
}

define i16 @test_vaddv_s16(<4 x i16> %a) {
; CHECK-SD-LABEL: test_vaddv_s16:
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: addv h0, v0.4h
; CHECK-SD-NEXT: fmov w0, s0
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: test_vaddv_s16:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: addv h0, v0.4h
; CHECK-GI-NEXT: smov w0, v0.h[0]
; CHECK-GI-NEXT: ret
entry:
%vaddv.i = tail call i32 @llvm.aarch64.neon.saddv.i32.v4i16(<4 x i16> %a)
%0 = trunc i32 %vaddv.i to i16
ret i16 %0
}

define i8 @test_vaddv_u8(<8 x i8> %a) {
; CHECK-SD-LABEL: test_vaddv_u8:
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: addv b0, v0.8b
; CHECK-SD-NEXT: fmov w0, s0
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: test_vaddv_u8:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: addv b0, v0.8b
; CHECK-GI-NEXT: smov w0, v0.b[0]
; CHECK-GI-NEXT: ret
entry:
%vaddv.i = tail call i32 @llvm.aarch64.neon.saddv.i32.v8i8(<8 x i8> %a)
%0 = trunc i32 %vaddv.i to i8
ret i8 %0
}

define i16 @test_vaddv_u16(<4 x i16> %a) {
; CHECK-SD-LABEL: test_vaddv_u16:
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: addv h0, v0.4h
; CHECK-SD-NEXT: fmov w0, s0
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: test_vaddv_u16:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: addv h0, v0.4h
; CHECK-GI-NEXT: smov w0, v0.h[0]
; CHECK-GI-NEXT: ret
entry:
%vaddv.i = tail call i32 @llvm.aarch64.neon.saddv.i32.v4i16(<4 x i16> %a)
%0 = trunc i32 %vaddv.i to i16
ret i16 %0
}

define i8 @test_vaddvq_s8(<16 x i8> %a) {
; CHECK-SD-LABEL: test_vaddvq_s8:
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: addv b0, v0.16b
; CHECK-SD-NEXT: fmov w0, s0
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: test_vaddvq_s8:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: addv b0, v0.16b
; CHECK-GI-NEXT: smov w0, v0.b[0]
; CHECK-GI-NEXT: ret
entry:
%vaddv.i = tail call i32 @llvm.aarch64.neon.saddv.i32.v16i8(<16 x i8> %a)
%0 = trunc i32 %vaddv.i to i8
ret i8 %0
}

define i16 @test_vaddvq_s16(<8 x i16> %a) {
; CHECK-SD-LABEL: test_vaddvq_s16:
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: addv h0, v0.8h
; CHECK-SD-NEXT: fmov w0, s0
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: test_vaddvq_s16:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: addv h0, v0.8h
; CHECK-GI-NEXT: smov w0, v0.h[0]
; CHECK-GI-NEXT: ret
entry:
%vaddv.i = tail call i32 @llvm.aarch64.neon.saddv.i32.v8i16(<8 x i16> %a)
%0 = trunc i32 %vaddv.i to i16
Expand All @@ -444,13 +598,35 @@ entry:
}

define i8 @test_vaddvq_u8(<16 x i8> %a) {
; CHECK-SD-LABEL: test_vaddvq_u8:
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: addv b0, v0.16b
; CHECK-SD-NEXT: fmov w0, s0
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: test_vaddvq_u8:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: addv b0, v0.16b
; CHECK-GI-NEXT: smov w0, v0.b[0]
; CHECK-GI-NEXT: ret
entry:
%vaddv.i = tail call i32 @llvm.aarch64.neon.saddv.i32.v16i8(<16 x i8> %a)
%0 = trunc i32 %vaddv.i to i8
ret i8 %0
}

define i16 @test_vaddvq_u16(<8 x i16> %a) {
; CHECK-SD-LABEL: test_vaddvq_u16:
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: addv h0, v0.8h
; CHECK-SD-NEXT: fmov w0, s0
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: test_vaddvq_u16:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: addv h0, v0.8h
; CHECK-GI-NEXT: smov w0, v0.h[0]
; CHECK-GI-NEXT: ret
entry:
%vaddv.i = tail call i32 @llvm.aarch64.neon.saddv.i32.v8i16(<8 x i16> %a)
%0 = trunc i32 %vaddv.i to i16
Expand Down

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