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[AMDGPU] Fix a case of updating LiveIntervals in SIOptimizeExecMaskin…
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…gPreRA

This was causing two test failures when I applied D129208 to enable
extra verification of LiveIntervals:

  LLVM :: CodeGen/AMDGPU/optimize-negated-cond-exec-masking-wave32.mir
  LLVM :: CodeGen/AMDGPU/optimize-negated-cond-exec-masking.mir

Differential Revision: https://reviews.llvm.org/D147721
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jayfoad committed Apr 8, 2023
1 parent 09fecbb commit 985e24c
Showing 1 changed file with 6 additions and 0 deletions.
6 changes: 6 additions & 0 deletions llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp
Expand Up @@ -294,7 +294,13 @@ bool SIOptimizeExecMaskingPreRA::optimizeVcndVcmpPair(MachineBasicBlock &MBB) {

LIS->removeVRegDefAt(*SelLI, SelIdx.getRegSlot());
LIS->RemoveMachineInstrFromMaps(*Sel);
bool ShrinkSel = Sel->getOperand(0).readsReg();
Sel->eraseFromParent();
if (ShrinkSel) {
// The result of the V_CNDMASK was a subreg def which counted as a read
// from the other parts of the reg. Shrink their live ranges.
LIS->shrinkToUses(SelLI);
}
}
}

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