Merging r259342 (with s/p2align 4/align 16) because r258750 is not in…

… 3.8. ------------------------------------------------------------------------ r259342 | ibreger | 2016-01-31 23:56:09 -0800 (Sun, 31 Jan 2016) | 3 lines AVX512 : Fix SETCCE lowering for KNL 32 bit. Differential Revision: http://reviews.llvm.org/D16752 ------------------------------------------------------------------------ llvm-svn: 259533
llvm · Feb 2, 2016 · 999896f · 999896f
1 parent fd3654f
commit 999896f
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Showing 2 changed files with 68 additions and 19 deletions.
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -1335,6 +1335,7 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
 
     setOperationAction(ISD::BR_CC,              MVT::i1,    Expand);
     setOperationAction(ISD::SETCC,              MVT::i1,    Custom);
+    setOperationAction(ISD::SETCCE,             MVT::i1,    Custom);
     setOperationAction(ISD::SELECT_CC,          MVT::i1,    Expand);
     setOperationAction(ISD::XOR,                MVT::i1,    Legal);
     setOperationAction(ISD::OR,                 MVT::i1,    Legal);
@@ -14975,8 +14976,11 @@ SDValue X86TargetLowering::LowerSETCCE(SDValue Op, SelectionDAG &DAG) const {
   assert(Carry.getOpcode() != ISD::CARRY_FALSE);
   SDVTList VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
   SDValue Cmp = DAG.getNode(X86ISD::SBB, DL, VTs, LHS, RHS, Carry);
-  return DAG.getNode(X86ISD::SETCC, DL, Op.getValueType(),
-                     DAG.getConstant(CC, DL, MVT::i8), Cmp.getValue(1));
+  SDValue SetCC = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
+                              DAG.getConstant(CC, DL, MVT::i8), Cmp.getValue(1));
+  if (Op.getSimpleValueType() == MVT::i1)
+      return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, SetCC);
+  return SetCC;
 }
 
 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.

diff --git a/llvm/test/CodeGen/X86/setcc-lowering.ll b/llvm/test/CodeGen/X86/setcc-lowering.ll
@@ -1,30 +1,75 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+avx < %s | FileCheck %s
+; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+avx < %s | FileCheck %s --check-prefix=AVX
+; RUN: llc -mtriple=i386-unknown-linux-gnu -mcpu=knl < %s   | FileCheck %s --check-prefix=KNL-32
+
 
 ; Verify that we don't crash during codegen due to a wrong lowering
 ; of a setcc node with illegal operand types and return type.
 
 define <8 x i16> @pr25080(<8 x i32> %a) {
-; CHECK-LABEL: pr25080:
-; CHECK:       # BB#0: # %entry
-; CHECK-NEXT:    vandps {{.*}}(%rip), %ymm0, %ymm0
-; CHECK-NEXT:    vextractf128 $1, %ymm0, %xmm1
-; CHECK-NEXT:    vpxor %xmm2, %xmm2, %xmm2
-; CHECK-NEXT:    vpcmpeqd %xmm2, %xmm1, %xmm1
-; CHECK-NEXT:    vmovdqa {{.*#+}} xmm3 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
-; CHECK-NEXT:    vpshufb %xmm3, %xmm1, %xmm1
-; CHECK-NEXT:    vpcmpeqd %xmm2, %xmm0, %xmm0
-; CHECK-NEXT:    vpshufb %xmm3, %xmm0, %xmm0
-; CHECK-NEXT:    vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
-; CHECK-NEXT:    vpor {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-NEXT:    vpsllw $15, %xmm0, %xmm0
-; CHECK-NEXT:    vpsraw $15, %xmm0, %xmm0
-; CHECK-NEXT:    vzeroupper
-; CHECK-NEXT:    retq
+; AVX-LABEL: pr25080:
+; AVX:       # BB#0: # %entry
+; AVX-NEXT:    vandps {{.*}}(%rip), %ymm0, %ymm0
+; AVX-NEXT:    vextractf128 $1, %ymm0, %xmm1
+; AVX-NEXT:    vpxor %xmm2, %xmm2, %xmm2
+; AVX-NEXT:    vpcmpeqd %xmm2, %xmm1, %xmm1
+; AVX-NEXT:    vmovdqa {{.*#+}} xmm3 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
+; AVX-NEXT:    vpshufb %xmm3, %xmm1, %xmm1
+; AVX-NEXT:    vpcmpeqd %xmm2, %xmm0, %xmm0
+; AVX-NEXT:    vpshufb %xmm3, %xmm0, %xmm0
+; AVX-NEXT:    vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; AVX-NEXT:    vpor {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT:    vpsllw $15, %xmm0, %xmm0
+; AVX-NEXT:    vpsraw $15, %xmm0, %xmm0
+; AVX-NEXT:    vzeroupper
+; AVX-NEXT:    retq
 entry:
   %0 = trunc <8 x i32> %a to <8 x i23>
   %1 = icmp eq <8 x i23> %0, zeroinitializer
   %2 = or <8 x i1> %1, <i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false>
   %3 = sext <8 x i1> %2 to <8 x i16>
   ret <8 x i16> %3
 }
+
+define void @pr26232(i64 %a) {
+; KNL-32-LABEL: pr26232:
+; KNL-32:       # BB#0: # %for_test11.preheader
+; KNL-32-NEXT:    pushl %esi
+; KNL-32-NEXT:  .Ltmp0:
+; KNL-32-NEXT:    .cfi_def_cfa_offset 8
+; KNL-32-NEXT:  .Ltmp1:
+; KNL-32-NEXT:    .cfi_offset %esi, -8
+; KNL-32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; KNL-32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; KNL-32-NEXT:    movw $-1, %dx
+; KNL-32-NEXT:    .align 16, 0x90
+; KNL-32-NEXT:  .LBB1_1: # %for_loop599
+; KNL-32-NEXT:    # =>This Inner Loop Header: Depth=1
+; KNL-32-NEXT:    cmpl $65536, %ecx # imm = 0x10000
+; KNL-32-NEXT:    movl %eax, %esi
+; KNL-32-NEXT:    sbbl $0, %esi
+; KNL-32-NEXT:    movl $0, %esi
+; KNL-32-NEXT:    cmovlw %dx, %si
+; KNL-32-NEXT:    testw %si, %si
+; KNL-32-NEXT:    jne .LBB1_1
+; KNL-32-NEXT:  # BB#2: # %for_exit600
+; KNL-32-NEXT:    popl %esi
+; KNL-32-NEXT:    retl
+allocas:
+  br label %for_test11.preheader
+
+for_test11.preheader:                             ; preds = %for_test11.preheader, %allocas
+  br i1 undef, label %for_loop599, label %for_test11.preheader
+
+for_loop599:                                      ; preds = %for_loop599, %for_test11.preheader
+  %less_i_load605_ = icmp slt i64 %a, 65536
+  %less_i_load605__broadcast_init = insertelement <16 x i1> undef, i1 %less_i_load605_, i32 0
+  %less_i_load605__broadcast = shufflevector <16 x i1> %less_i_load605__broadcast_init, <16 x i1> undef, <16 x i32> zeroinitializer
+  %"oldMask&test607" = and <16 x i1> %less_i_load605__broadcast, undef
+  %intmask.i894 = bitcast <16 x i1> %"oldMask&test607" to i16
+  %res.i895 = icmp eq i16 %intmask.i894, 0
+  br i1 %res.i895, label %for_exit600, label %for_loop599
+
+for_exit600:                                      ; preds = %for_loop599
+  ret void
+}