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[SystemZ] Add compare-and-branch instructions to MC
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This adds MC support for fused compare + indirect branch instructions,
ie. CRB, CGRB, CLRB, CLGRB, CIB, CGIB, CLIB, CLGIB. They aren't actually
generated yet -- this is preparation for their use for conditional
returns in the next iteration of D17339.

Author: koriakin
Differential Revision: http://reviews.llvm.org/D18742

llvm-svn: 265296
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@uweigand
uweigand committed Apr 4, 2016
1 parent 8e62db3 commit 99ac504
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Showing 4 changed files with 1,282 additions and 21 deletions.
37 changes: 37 additions & 0 deletions llvm/lib/Target/SystemZ/SystemZInstrFormats.td
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Original file line number Diff line number Diff line change
Expand Up @@ -260,6 +260,24 @@ class InstRIL<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
let Inst{31-0} = I2;
}

class InstRIS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
field bits<48> SoftFail = 0;

bits<4> R1;
bits<8> I2;
bits<4> M3;
bits<16> BD4;

let Inst{47-40} = op{15-8};
let Inst{39-36} = R1;
let Inst{35-32} = M3;
let Inst{31-16} = BD4;
let Inst{15-8} = I2;
let Inst{7-0} = op{7-0};
}

class InstRR<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<2, outs, ins, asmstr, pattern> {
field bits<16> Inst;
Expand Down Expand Up @@ -320,6 +338,25 @@ class InstRRF<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
let Inst{3-0} = R2;
}

class InstRRS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
field bits<48> SoftFail = 0;

bits<4> R1;
bits<4> R2;
bits<4> M3;
bits<16> BD4;

let Inst{47-40} = op{15-8};
let Inst{39-36} = R1;
let Inst{35-32} = R2;
let Inst{31-16} = BD4;
let Inst{15-12} = M3;
let Inst{11-8} = 0;
let Inst{7-0} = op{7-0};
}

class InstRX<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<4, outs, ins, asmstr, pattern> {
field bits<32> Inst;
Expand Down
90 changes: 69 additions & 21 deletions llvm/lib/Target/SystemZ/SystemZInstrInfo.td
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Original file line number Diff line number Diff line change
Expand Up @@ -110,6 +110,30 @@ multiclass CompareBranches<Operand ccmask, string pos1, string pos2> {
def LGIJ : InstRIEc<0xEC7D, (outs), (ins GR64:$R1, imm64zx8:$I2, ccmask:$M3,
brtarget16:$RI4),
"clgij"##pos1##"\t$R1, $I2, "##pos2##"$RI4", []>;
def RB : InstRRS<0xECF6, (outs), (ins GR32:$R1, GR32:$R2, ccmask:$M3,
bdaddr12only:$BD4),
"crb"##pos1##"\t$R1, $R2, "##pos2##"$BD4", []>;
def GRB : InstRRS<0xECE4, (outs), (ins GR64:$R1, GR64:$R2, ccmask:$M3,
bdaddr12only:$BD4),
"cgrb"##pos1##"\t$R1, $R2, "##pos2##"$BD4", []>;
def IB : InstRIS<0xECFE, (outs), (ins GR32:$R1, imm32sx8:$I2, ccmask:$M3,
bdaddr12only:$BD4),
"cib"##pos1##"\t$R1, $I2, "##pos2##"$BD4", []>;
def GIB : InstRIS<0xECFC, (outs), (ins GR64:$R1, imm64sx8:$I2, ccmask:$M3,
bdaddr12only:$BD4),
"cgib"##pos1##"\t$R1, $I2, "##pos2##"$BD4", []>;
def LRB : InstRRS<0xECF7, (outs), (ins GR32:$R1, GR32:$R2, ccmask:$M3,
bdaddr12only:$BD4),
"clrb"##pos1##"\t$R1, $R2, "##pos2##"$BD4", []>;
def LGRB : InstRRS<0xECE5, (outs), (ins GR64:$R1, GR64:$R2, ccmask:$M3,
bdaddr12only:$BD4),
"clgrb"##pos1##"\t$R1, $R2, "##pos2##"$BD4", []>;
def LIB : InstRIS<0xECFF, (outs), (ins GR32:$R1, imm32zx8:$I2, ccmask:$M3,
bdaddr12only:$BD4),
"clib"##pos1##"\t$R1, $I2, "##pos2##"$BD4", []>;
def LGIB : InstRIS<0xECFD, (outs), (ins GR64:$R1, imm64zx8:$I2, ccmask:$M3,
bdaddr12only:$BD4),
"clgib"##pos1##"\t$R1, $I2, "##pos2##"$BD4", []>;
}
}
let isCodeGenOnly = 1 in
Expand Down Expand Up @@ -157,30 +181,54 @@ defm AsmNO : CondExtendedMnemonic<14, "no">;
// we need the custom parsing routines to select the correct register class.
multiclass IntCondExtendedMnemonicA<bits<4> ccmask, string name> {
let isBranch = 1, isTerminator = 1, M3 = ccmask in {
def CR : InstRIEb<0xEC76, (outs), (ins GR32:$R1, GR32:$R2,
brtarget16:$RI4),
"crj"##name##"\t$R1, $R2, $RI4", []>;
def CGR : InstRIEb<0xEC64, (outs), (ins GR64:$R1, GR64:$R2,
brtarget16:$RI4),
"cgrj"##name##"\t$R1, $R2, $RI4", []>;
def CI : InstRIEc<0xEC7E, (outs), (ins GR32:$R1, imm32sx8:$I2,
brtarget16:$RI4),
"cij"##name##"\t$R1, $I2, $RI4", []>;
def CGI : InstRIEc<0xEC7C, (outs), (ins GR64:$R1, imm64sx8:$I2,
brtarget16:$RI4),
"cgij"##name##"\t$R1, $I2, $RI4", []>;
def CLR : InstRIEb<0xEC77, (outs), (ins GR32:$R1, GR32:$R2,
brtarget16:$RI4),
"clrj"##name##"\t$R1, $R2, $RI4", []>;
def CLGR : InstRIEb<0xEC65, (outs), (ins GR64:$R1, GR64:$R2,
def CRJ : InstRIEb<0xEC76, (outs), (ins GR32:$R1, GR32:$R2,
brtarget16:$RI4),
"crj"##name##"\t$R1, $R2, $RI4", []>;
def CGRJ : InstRIEb<0xEC64, (outs), (ins GR64:$R1, GR64:$R2,
brtarget16:$RI4),
"cgrj"##name##"\t$R1, $R2, $RI4", []>;
def CIJ : InstRIEc<0xEC7E, (outs), (ins GR32:$R1, imm32sx8:$I2,
brtarget16:$RI4),
"clgrj"##name##"\t$R1, $R2, $RI4", []>;
def CLI : InstRIEc<0xEC7F, (outs), (ins GR32:$R1, imm32zx8:$I2,
"cij"##name##"\t$R1, $I2, $RI4", []>;
def CGIJ : InstRIEc<0xEC7C, (outs), (ins GR64:$R1, imm64sx8:$I2,
brtarget16:$RI4),
"clij"##name##"\t$R1, $I2, $RI4", []>;
def CLGI : InstRIEc<0xEC7D, (outs), (ins GR64:$R1, imm64zx8:$I2,
"cgij"##name##"\t$R1, $I2, $RI4", []>;
def CLRJ : InstRIEb<0xEC77, (outs), (ins GR32:$R1, GR32:$R2,
brtarget16:$RI4),
"clgij"##name##"\t$R1, $I2, $RI4", []>;
"clrj"##name##"\t$R1, $R2, $RI4", []>;
def CLGRJ : InstRIEb<0xEC65, (outs), (ins GR64:$R1, GR64:$R2,
brtarget16:$RI4),
"clgrj"##name##"\t$R1, $R2, $RI4", []>;
def CLIJ : InstRIEc<0xEC7F, (outs), (ins GR32:$R1, imm32zx8:$I2,
brtarget16:$RI4),
"clij"##name##"\t$R1, $I2, $RI4", []>;
def CLGIJ : InstRIEc<0xEC7D, (outs), (ins GR64:$R1, imm64zx8:$I2,
brtarget16:$RI4),
"clgij"##name##"\t$R1, $I2, $RI4", []>;
def CRB : InstRRS<0xECF6, (outs), (ins GR32:$R1, GR32:$R2,
bdaddr12only:$BD4),
"crb"##name##"\t$R1, $R2, $BD4", []>;
def CGRB : InstRRS<0xECE4, (outs), (ins GR64:$R1, GR64:$R2,
bdaddr12only:$BD4),
"cgrb"##name##"\t$R1, $R2, $BD4", []>;
def CIB : InstRIS<0xECFE, (outs), (ins GR32:$R1, imm32sx8:$I2,
bdaddr12only:$BD4),
"cib"##name##"\t$R1, $I2, $BD4", []>;
def CGIB : InstRIS<0xECFC, (outs), (ins GR64:$R1, imm64sx8:$I2,
bdaddr12only:$BD4),
"cgib"##name##"\t$R1, $I2, $BD4", []>;
def CLRB : InstRRS<0xECF7, (outs), (ins GR32:$R1, GR32:$R2,
bdaddr12only:$BD4),
"clrb"##name##"\t$R1, $R2, $BD4", []>;
def CLGRB : InstRRS<0xECE5, (outs), (ins GR64:$R1, GR64:$R2,
bdaddr12only:$BD4),
"clgrb"##name##"\t$R1, $R2, $BD4", []>;
def CLIB : InstRIS<0xECFF, (outs), (ins GR32:$R1, imm32zx8:$I2,
bdaddr12only:$BD4),
"clib"##name##"\t$R1, $I2, $BD4", []>;
def CLGIB : InstRIS<0xECFD, (outs), (ins GR64:$R1, imm64zx8:$I2,
bdaddr12only:$BD4),
"clgib"##name##"\t$R1, $I2, $BD4", []>;
}
}
multiclass IntCondExtendedMnemonic<bits<4> ccmask, string name1, string name2>
Expand Down

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