[VE] Update floating-point arithmetic instructions

Summary:
Changing all mnemonic to match assembly instructions to simplify mnemonic
naming rules. This time update all floating-point arithmetic instructions.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D78768

llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.cpp

@@ -182,3 +182,9 @@ void VEInstPrinter::printCCOperand(const MCInst *MI, int OpNum,
   int CC = (int)MI->getOperand(OpNum).getImm();
   O << VECondCodeToString((VECC::CondCode)CC);
 }
+
+void VEInstPrinter::printRDOperand(const MCInst *MI, int OpNum,
+                                   const MCSubtargetInfo &STI, raw_ostream &O) {
+  int RD = (int)MI->getOperand(OpNum).getImm();
+  O << VERDToString((VERD::RoundingMode)RD);
+}

llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.h

@@ -51,6 +51,8 @@ class VEInstPrinter : public MCInstPrinter {
                         raw_ostream &OS);
   void printCCOperand(const MCInst *MI, int OpNum, const MCSubtargetInfo &STI,
                       raw_ostream &OS);
+  void printRDOperand(const MCInst *MI, int OpNum, const MCSubtargetInfo &STI,
+                      raw_ostream &OS);
 };
 } // namespace llvm
 

llvm/lib/Target/VE/VE.h

@@ -65,6 +65,19 @@ enum CondCode {
   CC_AT =    15 + 6, // Always
 };
 }
+// Enums corresponding to VE Rounding Mode.  These values must be kept in
+// sync with the ones in the .td file.
+namespace VERD {
+enum RoundingMode {
+  RD_NONE = 0, // According to PSW
+  RD_RZ = 8,   // Round toward Zero
+  RD_RP = 9,   // Round toward Plus infinity
+  RD_RM = 10,  // Round toward Minus infinity
+  RD_RN = 11,  // Round to Nearest (ties to Even)
+  RD_RA = 12,  // Round to Nearest (ties to Away)
+  UNKNOWN
+};
+}
 
 inline static const char *VECondCodeToString(VECC::CondCode CC) {
   switch (CC) {
@@ -94,6 +107,25 @@ inline static const char *VECondCodeToString(VECC::CondCode CC) {
   llvm_unreachable("Invalid cond code");
 }
 
+inline static const char *VERDToString(VERD::RoundingMode R) {
+  switch (R) {
+  case VERD::RD_NONE:
+    return "";
+  case VERD::RD_RZ:
+    return ".rz";
+  case VERD::RD_RP:
+    return ".rp";
+  case VERD::RD_RM:
+    return ".rm";
+  case VERD::RD_RN:
+    return ".rn";
+  case VERD::RD_RA:
+    return ".ra";
+  default:
+    llvm_unreachable("Invalid branch predicate");
+  }
+}
+
 inline unsigned M0(unsigned Val) { return Val + 64; }
 inline unsigned M1(unsigned Val) { return Val; }