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[PowerPC] Combine fptoint-store under strict cases
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Reviewed By: shchenz

Differential Revision: https://reviews.llvm.org/D141249
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@ecnelises
ecnelises committed Jun 5, 2023
1 parent 225cf64 commit 9e17e08
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Showing 3 changed files with 109 additions and 87 deletions.
21 changes: 11 additions & 10 deletions llvm/lib/Target/PowerPC/PPCISelLowering.cpp
View file
Expand Up @@ -15040,20 +15040,21 @@ SDValue PPCTargetLowering::expandVSXStoreForLE(SDNode *N,
// Handle DAG combine for STORE (FP_TO_INT F).
SDValue PPCTargetLowering::combineStoreFPToInt(SDNode *N,
DAGCombinerInfo &DCI) const {

SelectionDAG &DAG = DCI.DAG;
SDLoc dl(N);
unsigned Opcode = N->getOperand(1).getOpcode();
(void)Opcode;
bool Strict = N->getOperand(1)->isStrictFPOpcode();

assert((Opcode == ISD::FP_TO_SINT || Opcode == ISD::FP_TO_UINT)
assert((Opcode == ISD::FP_TO_SINT || Opcode == ISD::FP_TO_UINT ||
Opcode == ISD::STRICT_FP_TO_SINT || Opcode == ISD::STRICT_FP_TO_UINT)
&& "Not a FP_TO_INT Instruction!");

SDValue Val = N->getOperand(1).getOperand(0);
SDValue Val = N->getOperand(1).getOperand(Strict ? 1 : 0);
EVT Op1VT = N->getOperand(1).getValueType();
EVT ResVT = Val.getValueType();

if (!isTypeLegal(ResVT))
if (!Subtarget.hasVSX() || !Subtarget.hasFPCVT() || !isTypeLegal(ResVT))
return SDValue();

// Only perform combine for conversion to i64/i32 or power9 i16/i8.
Expand All @@ -15073,9 +15074,9 @@ SDValue PPCTargetLowering::combineStoreFPToInt(SDNode *N,

// Set number of bytes being converted.
unsigned ByteSize = Op1VT.getScalarSizeInBits() / 8;
SDValue Ops[] = { N->getOperand(0), Val, N->getOperand(2),
DAG.getIntPtrConstant(ByteSize, dl, false),
DAG.getValueType(Op1VT) };
SDValue Ops[] = {N->getOperand(0), Val, N->getOperand(2),
DAG.getIntPtrConstant(ByteSize, dl, false),
DAG.getValueType(Op1VT)};

Val = DAG.getMemIntrinsicNode(PPCISD::ST_VSR_SCAL_INT, dl,
DAG.getVTList(MVT::Other), Ops,
Expand Down Expand Up @@ -15516,9 +15517,9 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
EVT Op1VT = N->getOperand(1).getValueType();
unsigned Opcode = N->getOperand(1).getOpcode();

if ((Opcode == ISD::FP_TO_SINT || Opcode == ISD::FP_TO_UINT) &&
Subtarget.hasFPCVT()) {
SDValue Val= combineStoreFPToInt(N, DCI);
if (Opcode == ISD::FP_TO_SINT || Opcode == ISD::FP_TO_UINT ||
Opcode == ISD::STRICT_FP_TO_SINT || Opcode == ISD::STRICT_FP_TO_UINT) {
SDValue Val = combineStoreFPToInt(N, DCI);
if (Val)
return Val;
}
Expand Down
94 changes: 56 additions & 38 deletions llvm/test/CodeGen/PowerPC/fp-strict-conv.ll
View file
@@ -1,8 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
; RUN: < %s -mtriple=powerpc64-unknown-linux -mcpu=pwr8 | FileCheck %s
; RUN: < %s -mtriple=powerpc64-unknown-linux -mcpu=pwr8 | FileCheck %s \
; RUN: --check-prefixes=CHECK,P8
; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
; RUN: < %s -mtriple=powerpc64le-unknown-linux -mcpu=pwr9 | FileCheck %s
; RUN: < %s -mtriple=powerpc64le-unknown-linux -mcpu=pwr9 | FileCheck %s \
; RUN: --check-prefixes=CHECK,P9
; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
; RUN: < %s -mtriple=powerpc64le-unknown-linux -mcpu=pwr8 -mattr=-vsx | \
; RUN: FileCheck %s -check-prefix=NOVSX
Expand Down Expand Up @@ -330,8 +332,7 @@ define void @d_to_i32_store(double %m, ptr %addr) #0 {
; CHECK-LABEL: d_to_i32_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xscvdpsxws f0, f1
; CHECK-NEXT: mffprwz r3, f0
; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: stfiwx f0, 0, r4
; CHECK-NEXT: blr
;
; NOVSX-LABEL: d_to_i32_store:
Expand All @@ -349,12 +350,17 @@ entry:
}

define void @d_to_i64_store(double %m, ptr %addr) #0 {
; CHECK-LABEL: d_to_i64_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xscvdpsxds f0, f1
; CHECK-NEXT: mffprd r3, f0
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: blr
; P8-LABEL: d_to_i64_store:
; P8: # %bb.0: # %entry
; P8-NEXT: xscvdpsxds f0, f1
; P8-NEXT: stxsdx f0, 0, r4
; P8-NEXT: blr
;
; P9-LABEL: d_to_i64_store:
; P9: # %bb.0: # %entry
; P9-NEXT: xscvdpsxds v2, f1
; P9-NEXT: stxsd v2, 0(r4)
; P9-NEXT: blr
;
; NOVSX-LABEL: d_to_i64_store:
; NOVSX: # %bb.0: # %entry
Expand All @@ -370,12 +376,17 @@ entry:
}

define void @d_to_u64_store(double %m, ptr %addr) #0 {
; CHECK-LABEL: d_to_u64_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xscvdpuxds f0, f1
; CHECK-NEXT: mffprd r3, f0
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: blr
; P8-LABEL: d_to_u64_store:
; P8: # %bb.0: # %entry
; P8-NEXT: xscvdpuxds f0, f1
; P8-NEXT: stxsdx f0, 0, r4
; P8-NEXT: blr
;
; P9-LABEL: d_to_u64_store:
; P9: # %bb.0: # %entry
; P9-NEXT: xscvdpuxds v2, f1
; P9-NEXT: stxsd v2, 0(r4)
; P9-NEXT: blr
;
; NOVSX-LABEL: d_to_u64_store:
; NOVSX: # %bb.0: # %entry
Expand All @@ -394,8 +405,7 @@ define void @d_to_u32_store(double %m, ptr %addr) #0 {
; CHECK-LABEL: d_to_u32_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xscvdpuxws f0, f1
; CHECK-NEXT: mffprwz r3, f0
; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: stfiwx f0, 0, r4
; CHECK-NEXT: blr
;
; NOVSX-LABEL: d_to_u32_store:
Expand All @@ -416,8 +426,7 @@ define void @f_to_i32_store(float %m, ptr %addr) #0 {
; CHECK-LABEL: f_to_i32_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xscvdpsxws f0, f1
; CHECK-NEXT: mffprwz r3, f0
; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: stfiwx f0, 0, r4
; CHECK-NEXT: blr
;
; NOVSX-LABEL: f_to_i32_store:
Expand All @@ -435,12 +444,17 @@ entry:
}

define void @f_to_i64_store(float %m, ptr %addr) #0 {
; CHECK-LABEL: f_to_i64_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xscvdpsxds f0, f1
; CHECK-NEXT: mffprd r3, f0
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: blr
; P8-LABEL: f_to_i64_store:
; P8: # %bb.0: # %entry
; P8-NEXT: xscvdpsxds f0, f1
; P8-NEXT: stxsdx f0, 0, r4
; P8-NEXT: blr
;
; P9-LABEL: f_to_i64_store:
; P9: # %bb.0: # %entry
; P9-NEXT: xscvdpsxds v2, f1
; P9-NEXT: stxsd v2, 0(r4)
; P9-NEXT: blr
;
; NOVSX-LABEL: f_to_i64_store:
; NOVSX: # %bb.0: # %entry
Expand All @@ -456,12 +470,17 @@ entry:
}

define void @f_to_u64_store(float %m, ptr %addr) #0 {
; CHECK-LABEL: f_to_u64_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xscvdpuxds f0, f1
; CHECK-NEXT: mffprd r3, f0
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: blr
; P8-LABEL: f_to_u64_store:
; P8: # %bb.0: # %entry
; P8-NEXT: xscvdpuxds f0, f1
; P8-NEXT: stxsdx f0, 0, r4
; P8-NEXT: blr
;
; P9-LABEL: f_to_u64_store:
; P9: # %bb.0: # %entry
; P9-NEXT: xscvdpuxds v2, f1
; P9-NEXT: stxsd v2, 0(r4)
; P9-NEXT: blr
;
; NOVSX-LABEL: f_to_u64_store:
; NOVSX: # %bb.0: # %entry
Expand All @@ -480,8 +499,7 @@ define void @f_to_u32_store(float %m, ptr %addr) #0 {
; CHECK-LABEL: f_to_u32_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xscvdpuxws f0, f1
; CHECK-NEXT: mffprwz r3, f0
; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: stfiwx f0, 0, r4
; CHECK-NEXT: blr
;
; NOVSX-LABEL: f_to_u32_store:
Expand Down Expand Up @@ -646,8 +664,8 @@ define void @fptoint_nofpexcept_f64(double %m, ptr %addr1, ptr %addr2) {
; MIR-LABEL: name: fptoint_nofpexcept_f64
; MIR: renamable $f{{[0-9]+}} = nofpexcept XSCVDPSXWS
; MIR: renamable $f{{[0-9]+}} = nofpexcept XSCVDPUXWS
; MIR: renamable $f{{[0-9]+}} = nofpexcept XSCVDPSXDS
; MIR: renamable $f{{[0-9]+}} = nofpexcept XSCVDPUXDS
; MIR: renamable $vf{{[0-9]+}} = nofpexcept XSCVDPSXDS
; MIR: renamable $vf{{[0-9]+}} = nofpexcept XSCVDPUXDS
entry:
%conv1 = tail call i32 @llvm.experimental.constrained.fptosi.i32.f64(double %m, metadata !"fpexcept.ignore") #0
%conv2 = tail call i32 @llvm.experimental.constrained.fptoui.i32.f64(double %m, metadata !"fpexcept.ignore") #0
Expand All @@ -664,8 +682,8 @@ define void @fptoint_nofpexcept_f32(float %m, ptr %addr1, ptr %addr2) {
; MIR-LABEL: name: fptoint_nofpexcept_f32
; MIR: renamable $f{{[0-9]+}} = nofpexcept XSCVDPSXWS
; MIR: renamable $f{{[0-9]+}} = nofpexcept XSCVDPUXWS
; MIR: renamable $f{{[0-9]+}} = nofpexcept XSCVDPSXDS
; MIR: renamable $f{{[0-9]+}} = nofpexcept XSCVDPUXDS
; MIR: renamable $vf{{[0-9]+}} = nofpexcept XSCVDPSXDS
; MIR: renamable $vf{{[0-9]+}} = nofpexcept XSCVDPUXDS
entry:
%conv1 = tail call i32 @llvm.experimental.constrained.fptosi.i32.f32(float %m, metadata !"fpexcept.ignore") #0
%conv2 = tail call i32 @llvm.experimental.constrained.fptoui.i32.f32(float %m, metadata !"fpexcept.ignore") #0
Expand Down
81 changes: 42 additions & 39 deletions llvm/test/CodeGen/PowerPC/nofpexcept.ll
View file
Expand Up @@ -10,8 +10,8 @@ define i32 @fcmpu(double %a, double %b) {
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:f8rc = COPY $f2
; CHECK-NEXT: [[COPY1:%[0-9]+]]:f8rc = COPY $f1
; CHECK-NEXT: %2:crrc = nofpexcept FCMPUD [[COPY1]], [[COPY]]
; CHECK-NEXT: [[COPY2:%[0-9]+]]:crbitrc = COPY %2.sub_gt
; CHECK-NEXT: [[FCMPUD:%[0-9]+]]:crrc = nofpexcept FCMPUD [[COPY1]], [[COPY]]
; CHECK-NEXT: [[COPY2:%[0-9]+]]:crbitrc = COPY [[FCMPUD]].sub_gt
; CHECK-NEXT: [[LI8_:%[0-9]+]]:g8rc_and_g8rc_nox0 = LI8 0
; CHECK-NEXT: [[LI8_1:%[0-9]+]]:g8rc_and_g8rc_nox0 = LI8 1
; CHECK-NEXT: [[ISEL8_:%[0-9]+]]:g8rc = ISEL8 [[LI8_1]], [[LI8_]], [[COPY2]]
Expand All @@ -30,8 +30,8 @@ define double @max_typec(double %a, double %b) {
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vsfrc = COPY $f2
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vsfrc = COPY $f1
; CHECK-NEXT: %2:vsfrc = nofpexcept XSMAXCDP [[COPY1]], [[COPY]]
; CHECK-NEXT: $f1 = COPY %2
; CHECK-NEXT: [[XSMAXCDP:%[0-9]+]]:vsfrc = nofpexcept XSMAXCDP [[COPY1]], [[COPY]]
; CHECK-NEXT: $f1 = COPY [[XSMAXCDP]]
; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $f1
entry:
%cmp = fcmp ogt double %a, %b
Expand Down Expand Up @@ -80,42 +80,45 @@ define void @fptoint_nofpexcept(ppc_fp128 %p, fp128 %m, ptr %addr1, ptr %addr2)
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vrrc = COPY $v2
; CHECK-NEXT: [[COPY3:%[0-9]+]]:f8rc = COPY $f2
; CHECK-NEXT: [[COPY4:%[0-9]+]]:f8rc = COPY $f1
; CHECK-NEXT: %5:vrrc = nofpexcept XSCVQPSWZ [[COPY2]]
; CHECK-NEXT: [[COPY5:%[0-9]+]]:vslrc = COPY %5
; CHECK-NEXT: [[COPY6:%[0-9]+]]:vfrc = COPY [[COPY5]].sub_64
; CHECK-NEXT: [[MFVSRWZ:%[0-9]+]]:gprc = MFVSRWZ killed [[COPY6]]
; CHECK-NEXT: STW killed [[MFVSRWZ]], 0, [[COPY1]] :: (volatile store (s32) into %ir.addr1)
; CHECK-NEXT: %8:vrrc = nofpexcept XSCVQPUWZ [[COPY2]]
; CHECK-NEXT: [[COPY7:%[0-9]+]]:vslrc = COPY %8
; CHECK-NEXT: [[COPY8:%[0-9]+]]:vfrc = COPY [[COPY7]].sub_64
; CHECK-NEXT: [[MFVSRWZ1:%[0-9]+]]:gprc = MFVSRWZ killed [[COPY8]]
; CHECK-NEXT: STW killed [[MFVSRWZ1]], 0, [[COPY1]] :: (volatile store (s32) into %ir.addr1)
; CHECK-NEXT: %11:vrrc = nofpexcept XSCVQPSDZ [[COPY2]]
; CHECK-NEXT: %12:g8rc = nofpexcept MFVRD killed %11
; CHECK-NEXT: STD killed %12, 0, [[COPY]] :: (volatile store (s64) into %ir.addr2)
; CHECK-NEXT: %13:vrrc = nofpexcept XSCVQPUDZ [[COPY2]]
; CHECK-NEXT: %14:g8rc = nofpexcept MFVRD killed %13
; CHECK-NEXT: STD killed %14, 0, [[COPY]] :: (volatile store (s64) into %ir.addr2)
; CHECK-NEXT: [[XSCVQPSWZ:%[0-9]+]]:vrrc = nofpexcept XSCVQPSWZ [[COPY2]]
; CHECK-NEXT: [[COPY5:%[0-9]+]]:vslrc = COPY [[XSCVQPSWZ]]
; CHECK-NEXT: [[COPY6:%[0-9]+]]:vsfrc = COPY [[COPY5]].sub_64
; CHECK-NEXT: STIWX killed [[COPY6]], $zero8, [[COPY1]]
; CHECK-NEXT: [[XSCVQPUWZ:%[0-9]+]]:vrrc = nofpexcept XSCVQPUWZ [[COPY2]]
; CHECK-NEXT: [[COPY7:%[0-9]+]]:vslrc = COPY [[XSCVQPUWZ]]
; CHECK-NEXT: [[COPY8:%[0-9]+]]:vsfrc = COPY [[COPY7]].sub_64
; CHECK-NEXT: STIWX killed [[COPY8]], $zero8, [[COPY1]]
; CHECK-NEXT: [[XSCVQPSDZ:%[0-9]+]]:vrrc = nofpexcept XSCVQPSDZ [[COPY2]]
; CHECK-NEXT: [[MFVRD:%[0-9]+]]:g8rc = nofpexcept MFVRD killed [[XSCVQPSDZ]]
; CHECK-NEXT: [[XSCVQPSDZ1:%[0-9]+]]:vrrc = nofpexcept XSCVQPSDZ [[COPY2]]
; CHECK-NEXT: [[COPY9:%[0-9]+]]:vslrc = COPY [[XSCVQPSDZ1]]
; CHECK-NEXT: [[COPY10:%[0-9]+]]:vfrc = COPY [[COPY9]].sub_64
; CHECK-NEXT: STXSD killed [[COPY10]], 0, [[COPY]]
; CHECK-NEXT: [[XSCVQPUDZ:%[0-9]+]]:vrrc = nofpexcept XSCVQPUDZ [[COPY2]]
; CHECK-NEXT: [[MFVRD1:%[0-9]+]]:g8rc = nofpexcept MFVRD killed [[XSCVQPUDZ]]
; CHECK-NEXT: [[XSCVQPUDZ1:%[0-9]+]]:vrrc = nofpexcept XSCVQPUDZ [[COPY2]]
; CHECK-NEXT: [[COPY11:%[0-9]+]]:vslrc = COPY [[XSCVQPUDZ1]]
; CHECK-NEXT: [[COPY12:%[0-9]+]]:vfrc = COPY [[COPY11]].sub_64
; CHECK-NEXT: STXSD killed [[COPY12]], 0, [[COPY]]
; CHECK-NEXT: [[MFFS:%[0-9]+]]:f8rc = MFFS implicit $rm
; CHECK-NEXT: MTFSB1 31, implicit-def $rm, implicit-def $rm
; CHECK-NEXT: MTFSB0 30, implicit-def $rm, implicit-def $rm
; CHECK-NEXT: %15:f8rc = nofpexcept FADD [[COPY3]], [[COPY4]], implicit $rm
; CHECK-NEXT: [[FADD:%[0-9]+]]:f8rc = nofpexcept FADD [[COPY3]], [[COPY4]], implicit $rm
; CHECK-NEXT: MTFSFb 1, [[MFFS]], implicit-def $rm
; CHECK-NEXT: %16:vsfrc = nofpexcept XSCVDPSXWS killed %15, implicit $rm
; CHECK-NEXT: [[MFVSRWZ2:%[0-9]+]]:gprc = MFVSRWZ killed %16
; CHECK-NEXT: STW killed [[MFVSRWZ2]], 0, [[COPY1]] :: (volatile store (s32) into %ir.addr1)
; CHECK-NEXT: [[XSCVDPSXWS:%[0-9]+]]:vsfrc = nofpexcept XSCVDPSXWS killed [[FADD]], implicit $rm
; CHECK-NEXT: STIWX killed [[XSCVDPSXWS]], $zero8, [[COPY1]]
; CHECK-NEXT: [[ADDIStocHA8_:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDIStocHA8 $x2, %const.0
; CHECK-NEXT: [[DFLOADf32_:%[0-9]+]]:vssrc = DFLOADf32 target-flags(ppc-toc-lo) %const.0, killed [[ADDIStocHA8_]] :: (load (s32) from constant-pool)
; CHECK-NEXT: [[COPY9:%[0-9]+]]:f8rc = COPY [[DFLOADf32_]]
; CHECK-NEXT: [[FCMPOD:%[0-9]+]]:crrc = FCMPOD [[COPY4]], [[COPY9]]
; CHECK-NEXT: [[COPY10:%[0-9]+]]:crbitrc = COPY [[FCMPOD]].sub_eq
; CHECK-NEXT: [[COPY13:%[0-9]+]]:f8rc = COPY [[DFLOADf32_]]
; CHECK-NEXT: [[FCMPOD:%[0-9]+]]:crrc = FCMPOD [[COPY4]], [[COPY13]]
; CHECK-NEXT: [[COPY14:%[0-9]+]]:crbitrc = COPY [[FCMPOD]].sub_eq
; CHECK-NEXT: [[XXLXORdpz:%[0-9]+]]:f8rc = XXLXORdpz
; CHECK-NEXT: [[FCMPOD1:%[0-9]+]]:crrc = FCMPOD [[COPY3]], [[XXLXORdpz]]
; CHECK-NEXT: [[COPY11:%[0-9]+]]:crbitrc = COPY [[FCMPOD1]].sub_lt
; CHECK-NEXT: [[CRAND:%[0-9]+]]:crbitrc = CRAND killed [[COPY10]], killed [[COPY11]]
; CHECK-NEXT: [[COPY12:%[0-9]+]]:crbitrc = COPY [[FCMPOD]].sub_eq
; CHECK-NEXT: [[COPY13:%[0-9]+]]:crbitrc = COPY [[FCMPOD]].sub_lt
; CHECK-NEXT: [[CRANDC:%[0-9]+]]:crbitrc = CRANDC killed [[COPY13]], killed [[COPY12]]
; CHECK-NEXT: [[COPY15:%[0-9]+]]:crbitrc = COPY [[FCMPOD1]].sub_lt
; CHECK-NEXT: [[CRAND:%[0-9]+]]:crbitrc = CRAND killed [[COPY14]], killed [[COPY15]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:crbitrc = COPY [[FCMPOD]].sub_eq
; CHECK-NEXT: [[COPY17:%[0-9]+]]:crbitrc = COPY [[FCMPOD]].sub_lt
; CHECK-NEXT: [[CRANDC:%[0-9]+]]:crbitrc = CRANDC killed [[COPY17]], killed [[COPY16]]
; CHECK-NEXT: [[CROR:%[0-9]+]]:crbitrc = CROR killed [[CRANDC]], killed [[CRAND]]
; CHECK-NEXT: [[LIS:%[0-9]+]]:gprc_and_gprc_nor0 = LIS 32768
; CHECK-NEXT: [[LI:%[0-9]+]]:gprc_and_gprc_nor0 = LI 0
Expand All @@ -127,24 +130,24 @@ define void @fptoint_nofpexcept(ppc_fp128 %p, fp128 %m, ptr %addr1, ptr %addr2)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.entry:
; CHECK-NEXT: [[PHI:%[0-9]+]]:f8rc = PHI [[COPY9]], %bb.1, [[XXLXORdpz]], %bb.0
; CHECK-NEXT: [[PHI:%[0-9]+]]:f8rc = PHI [[COPY13]], %bb.1, [[XXLXORdpz]], %bb.0
; CHECK-NEXT: ADJCALLSTACKDOWN 32, 0, implicit-def dead $r1, implicit $r1
; CHECK-NEXT: $f1 = COPY [[COPY4]]
; CHECK-NEXT: $f2 = COPY [[COPY3]]
; CHECK-NEXT: $f3 = COPY [[PHI]]
; CHECK-NEXT: $f4 = COPY [[XXLXORdpz]]
; CHECK-NEXT: BL8_NOP &__gcc_qsub, csr_ppc64_altivec, implicit-def dead $lr8, implicit $rm, implicit $f1, implicit $f2, implicit $f3, implicit $f4, implicit $x2, implicit-def $r1, implicit-def $f1, implicit-def $f2
; CHECK-NEXT: ADJCALLSTACKUP 32, 0, implicit-def dead $r1, implicit $r1
; CHECK-NEXT: [[COPY14:%[0-9]+]]:f8rc = COPY $f1
; CHECK-NEXT: [[COPY15:%[0-9]+]]:f8rc = COPY $f2
; CHECK-NEXT: [[COPY18:%[0-9]+]]:f8rc = COPY $f1
; CHECK-NEXT: [[COPY19:%[0-9]+]]:f8rc = COPY $f2
; CHECK-NEXT: [[MFFS1:%[0-9]+]]:f8rc = MFFS implicit $rm
; CHECK-NEXT: MTFSB1 31, implicit-def $rm, implicit-def $rm
; CHECK-NEXT: MTFSB0 30, implicit-def $rm, implicit-def $rm
; CHECK-NEXT: %37:f8rc = nofpexcept FADD [[COPY15]], [[COPY14]], implicit $rm
; CHECK-NEXT: [[FADD1:%[0-9]+]]:f8rc = nofpexcept FADD [[COPY19]], [[COPY18]], implicit $rm
; CHECK-NEXT: MTFSFb 1, [[MFFS1]], implicit-def $rm
; CHECK-NEXT: %38:vsfrc = nofpexcept XSCVDPSXWS killed %37, implicit $rm
; CHECK-NEXT: [[MFVSRWZ3:%[0-9]+]]:gprc = MFVSRWZ killed %38
; CHECK-NEXT: [[XOR:%[0-9]+]]:gprc = XOR killed [[MFVSRWZ3]], killed [[ISEL]]
; CHECK-NEXT: [[XSCVDPSXWS1:%[0-9]+]]:vsfrc = nofpexcept XSCVDPSXWS killed [[FADD1]], implicit $rm
; CHECK-NEXT: [[MFVSRWZ:%[0-9]+]]:gprc = MFVSRWZ killed [[XSCVDPSXWS1]]
; CHECK-NEXT: [[XOR:%[0-9]+]]:gprc = XOR killed [[MFVSRWZ]], killed [[ISEL]]
; CHECK-NEXT: STW killed [[XOR]], 0, [[COPY1]] :: (volatile store (s32) into %ir.addr1)
; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm
entry:
Expand Down

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