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[Clang][SVE2.1] Add builtins for 2-way svdot (vectors, indexed)
As described in: ARM-software/acle#257 Patch by: David Sherwood <david.sherwood@arm.com> Reviewed By: dtemirbulatov Differential Revision: https://reviews.llvm.org/D151439
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clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_dot.c
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// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py | ||
// REQUIRES: aarch64-registered-target | ||
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s | ||
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK | ||
// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s | ||
// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK | ||
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s | ||
#include <arm_sve.h> | ||
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#ifdef SVE_OVERLOADED_FORMS | ||
// A simple used,unused... macro, long enough to represent any SVE builtin. | ||
#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3) A1##A3 | ||
#else | ||
#define SVE_ACLE_FUNC(A1,A2,A3) A1##A2##A3 | ||
#endif | ||
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// CHECK-LABEL: @test_svdot_s32_x2( | ||
// CHECK-NEXT: entry: | ||
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sdot.x2.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]]) | ||
// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]] | ||
// | ||
// CPP-CHECK-LABEL: @_Z17test_svdot_s32_x2u11__SVInt32_tu11__SVInt16_tu11__SVInt16_t( | ||
// CPP-CHECK-NEXT: entry: | ||
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sdot.x2.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]]) | ||
// CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]] | ||
// | ||
svint32_t test_svdot_s32_x2(svint32_t op1, svint16_t op2, svint16_t op3) | ||
{ | ||
return SVE_ACLE_FUNC(svdot,_s32_s16_s16,)(op1, op2, op3); | ||
} | ||
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// CHECK-LABEL: @test_svdot_u32_x2( | ||
// CHECK-NEXT: entry: | ||
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.udot.x2.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]]) | ||
// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]] | ||
// | ||
// CPP-CHECK-LABEL: @_Z17test_svdot_u32_x2u12__SVUint32_tu12__SVUint16_tu12__SVUint16_t( | ||
// CPP-CHECK-NEXT: entry: | ||
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.udot.x2.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]]) | ||
// CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]] | ||
// | ||
svuint32_t test_svdot_u32_x2(svuint32_t op1, svuint16_t op2, svuint16_t op3) | ||
{ | ||
return SVE_ACLE_FUNC(svdot,_u32_u16_u16,)(op1, op2, op3); | ||
} | ||
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// CHECK-LABEL: @test_svdot_f32_x2( | ||
// CHECK-NEXT: entry: | ||
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.fdot.x2.nxv4f32(<vscale x 4 x float> [[OP1:%.*]], <vscale x 8 x half> [[OP2:%.*]], <vscale x 8 x half> [[OP3:%.*]]) | ||
// CHECK-NEXT: ret <vscale x 4 x float> [[TMP0]] | ||
// | ||
// CPP-CHECK-LABEL: @_Z17test_svdot_f32_x2u13__SVFloat32_tu13__SVFloat16_tu13__SVFloat16_t( | ||
// CPP-CHECK-NEXT: entry: | ||
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.fdot.x2.nxv4f32(<vscale x 4 x float> [[OP1:%.*]], <vscale x 8 x half> [[OP2:%.*]], <vscale x 8 x half> [[OP3:%.*]]) | ||
// CPP-CHECK-NEXT: ret <vscale x 4 x float> [[TMP0]] | ||
// | ||
svfloat32_t test_svdot_f32_x2(svfloat32_t op1, svfloat16_t op2, svfloat16_t op3) | ||
{ | ||
return SVE_ACLE_FUNC(svdot,_f32_f16_f16,)(op1, op2, op3); | ||
} | ||
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// CHECK-LABEL: @test_svdot_lane_s32_x2( | ||
// CHECK-NEXT: entry: | ||
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sdot.lane.x2.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]], i32 3) | ||
// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]] | ||
// | ||
// CPP-CHECK-LABEL: @_Z22test_svdot_lane_s32_x2u11__SVInt32_tu11__SVInt16_tu11__SVInt16_t( | ||
// CPP-CHECK-NEXT: entry: | ||
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sdot.lane.x2.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]], i32 3) | ||
// CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]] | ||
// | ||
svint32_t test_svdot_lane_s32_x2(svint32_t op1, svint16_t op2, svint16_t op3) | ||
{ | ||
return SVE_ACLE_FUNC(svdot_lane,_s32_s16_s16,)(op1, op2, op3, 3); | ||
} | ||
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// CHECK-LABEL: @test_svdot_lane_u32_x2( | ||
// CHECK-NEXT: entry: | ||
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.udot.lane.x2.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]], i32 3) | ||
// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]] | ||
// | ||
// CPP-CHECK-LABEL: @_Z22test_svdot_lane_u32_x2u12__SVUint32_tu12__SVUint16_tu12__SVUint16_t( | ||
// CPP-CHECK-NEXT: entry: | ||
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.udot.lane.x2.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]], i32 3) | ||
// CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]] | ||
// | ||
svuint32_t test_svdot_lane_u32_x2(svuint32_t op1, svuint16_t op2, svuint16_t op3) | ||
{ | ||
return SVE_ACLE_FUNC(svdot_lane,_u32_u16_u16,)(op1, op2, op3, 3); | ||
} | ||
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// CHECK-LABEL: @test_svdot_lane_f32_x2( | ||
// CHECK-NEXT: entry: | ||
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.fdot.lane.x2.nxv4f32(<vscale x 4 x float> [[OP1:%.*]], <vscale x 8 x half> [[OP2:%.*]], <vscale x 8 x half> [[OP3:%.*]], i32 3) | ||
// CHECK-NEXT: ret <vscale x 4 x float> [[TMP0]] | ||
// | ||
// CPP-CHECK-LABEL: @_Z22test_svdot_lane_f32_x2u13__SVFloat32_tu13__SVFloat16_tu13__SVFloat16_t( | ||
// CPP-CHECK-NEXT: entry: | ||
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.fdot.lane.x2.nxv4f32(<vscale x 4 x float> [[OP1:%.*]], <vscale x 8 x half> [[OP2:%.*]], <vscale x 8 x half> [[OP3:%.*]], i32 3) | ||
// CPP-CHECK-NEXT: ret <vscale x 4 x float> [[TMP0]] | ||
// | ||
svfloat32_t test_svdot_lane_f32_x2(svfloat32_t op1, svfloat16_t op2, svfloat16_t op3) | ||
{ | ||
return SVE_ACLE_FUNC(svdot_lane,_f32_f16_f16,)(op1, op2, op3, 3); | ||
} |
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