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[clang-format] Indent Verilog case statements with comments (#71353)
If a line contains a comment outside of (fake) parentheses, the part following it is indented according to `CurrentState.Indent`. A Verilog case label and the statement that follows are broken with mustBreakBefore. So the part that follows the case label needs some special handling. Previously, that variable was left out. So the indentation was wrong when there was a comment. old: ```Verilog case (data) 16'd0: result = // 10'b0111111111; endcase case (data) 16'd0: // // result = // 10'b0111111111; endcase ``` new: ```Verilog case (data) 16'd0: result = // 10'b0111111111; endcase case (data) 16'd0: // // result = // 10'b0111111111; endcase ```
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