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[LoongArch] Add codegen support for icmp/fcmp with lsx/lasx fetaures (#…
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…74700)

Mark ISD::SETCC node as legal, and add handling for the vector types
condition codes.
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@wangleiat
wangleiat committed Dec 7, 2023
1 parent b396e54 commit 9ff7d0e
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14 changes: 14 additions & 0 deletions llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -247,6 +247,7 @@ LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Legal);
setOperationAction(ISD::BUILD_VECTOR, VT, Custom);

setOperationAction(ISD::SETCC, VT, Legal);
setOperationAction(ISD::VSELECT, VT, Legal);
}
for (MVT VT : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64}) {
Expand All @@ -260,11 +261,17 @@ LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM,
setOperationAction({ISD::SHL, ISD::SRA, ISD::SRL}, VT, Legal);
setOperationAction({ISD::CTPOP, ISD::CTLZ}, VT, Legal);
setOperationAction({ISD::MULHS, ISD::MULHU}, VT, Legal);
setCondCodeAction(
{ISD::SETNE, ISD::SETGE, ISD::SETGT, ISD::SETUGE, ISD::SETUGT}, VT,
Expand);
}
for (MVT VT : {MVT::v4f32, MVT::v2f64}) {
setOperationAction({ISD::FADD, ISD::FSUB}, VT, Legal);
setOperationAction({ISD::FMUL, ISD::FDIV}, VT, Legal);
setOperationAction(ISD::FMA, VT, Legal);
setCondCodeAction({ISD::SETGE, ISD::SETGT, ISD::SETOGE, ISD::SETOGT,
ISD::SETUGE, ISD::SETUGT},
VT, Expand);
}
}

Expand All @@ -280,6 +287,7 @@ LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Legal);
setOperationAction(ISD::BUILD_VECTOR, VT, Custom);

setOperationAction(ISD::SETCC, VT, Legal);
setOperationAction(ISD::VSELECT, VT, Legal);
}
for (MVT VT : {MVT::v4i64, MVT::v8i32, MVT::v16i16, MVT::v32i8}) {
Expand All @@ -293,11 +301,17 @@ LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM,
setOperationAction({ISD::SHL, ISD::SRA, ISD::SRL}, VT, Legal);
setOperationAction({ISD::CTPOP, ISD::CTLZ}, VT, Legal);
setOperationAction({ISD::MULHS, ISD::MULHU}, VT, Legal);
setCondCodeAction(
{ISD::SETNE, ISD::SETGE, ISD::SETGT, ISD::SETUGE, ISD::SETUGT}, VT,
Expand);
}
for (MVT VT : {MVT::v8f32, MVT::v4f64}) {
setOperationAction({ISD::FADD, ISD::FSUB}, VT, Legal);
setOperationAction({ISD::FMUL, ISD::FDIV}, VT, Legal);
setOperationAction(ISD::FMA, VT, Legal);
setCondCodeAction({ISD::SETGE, ISD::SETGT, ISD::SETOGE, ISD::SETOGT,
ISD::SETUGE, ISD::SETUGT},
VT, Expand);
}
}

Expand Down
95 changes: 95 additions & 0 deletions llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
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Original file line number Diff line number Diff line change
Expand Up @@ -1184,6 +1184,65 @@ multiclass PatShiftXrUimm<SDPatternOperator OpNode, string Inst> {
(!cast<LAInst>(Inst#"_D") LASX256:$xj, uimm6:$imm)>;
}

multiclass PatCCXrSimm5<CondCode CC, string Inst> {
def : Pat<(v32i8 (setcc (v32i8 LASX256:$xj),
(v32i8 (SplatPat_simm5 simm5:$imm)), CC)),
(!cast<LAInst>(Inst#"_B") LASX256:$xj, simm5:$imm)>;
def : Pat<(v16i16 (setcc (v16i16 LASX256:$xj),
(v16i16 (SplatPat_simm5 simm5:$imm)), CC)),
(!cast<LAInst>(Inst#"_H") LASX256:$xj, simm5:$imm)>;
def : Pat<(v8i32 (setcc (v8i32 LASX256:$xj),
(v8i32 (SplatPat_simm5 simm5:$imm)), CC)),
(!cast<LAInst>(Inst#"_W") LASX256:$xj, simm5:$imm)>;
def : Pat<(v4i64 (setcc (v4i64 LASX256:$xj),
(v4i64 (SplatPat_simm5 simm5:$imm)), CC)),
(!cast<LAInst>(Inst#"_D") LASX256:$xj, simm5:$imm)>;
}

multiclass PatCCXrUimm5<CondCode CC, string Inst> {
def : Pat<(v32i8 (setcc (v32i8 LASX256:$xj),
(v32i8 (SplatPat_uimm5 uimm5:$imm)), CC)),
(!cast<LAInst>(Inst#"_BU") LASX256:$xj, uimm5:$imm)>;
def : Pat<(v16i16 (setcc (v16i16 LASX256:$xj),
(v16i16 (SplatPat_uimm5 uimm5:$imm)), CC)),
(!cast<LAInst>(Inst#"_HU") LASX256:$xj, uimm5:$imm)>;
def : Pat<(v8i32 (setcc (v8i32 LASX256:$xj),
(v8i32 (SplatPat_uimm5 uimm5:$imm)), CC)),
(!cast<LAInst>(Inst#"_WU") LASX256:$xj, uimm5:$imm)>;
def : Pat<(v4i64 (setcc (v4i64 LASX256:$xj),
(v4i64 (SplatPat_uimm5 uimm5:$imm)), CC)),
(!cast<LAInst>(Inst#"_DU") LASX256:$xj, uimm5:$imm)>;
}

multiclass PatCCXrXr<CondCode CC, string Inst> {
def : Pat<(v32i8 (setcc (v32i8 LASX256:$xj), (v32i8 LASX256:$xk), CC)),
(!cast<LAInst>(Inst#"_B") LASX256:$xj, LASX256:$xk)>;
def : Pat<(v16i16 (setcc (v16i16 LASX256:$xj), (v16i16 LASX256:$xk), CC)),
(!cast<LAInst>(Inst#"_H") LASX256:$xj, LASX256:$xk)>;
def : Pat<(v8i32 (setcc (v8i32 LASX256:$xj), (v8i32 LASX256:$xk), CC)),
(!cast<LAInst>(Inst#"_W") LASX256:$xj, LASX256:$xk)>;
def : Pat<(v4i64 (setcc (v4i64 LASX256:$xj), (v4i64 LASX256:$xk), CC)),
(!cast<LAInst>(Inst#"_D") LASX256:$xj, LASX256:$xk)>;
}

multiclass PatCCXrXrU<CondCode CC, string Inst> {
def : Pat<(v32i8 (setcc (v32i8 LASX256:$xj), (v32i8 LASX256:$xk), CC)),
(!cast<LAInst>(Inst#"_BU") LASX256:$xj, LASX256:$xk)>;
def : Pat<(v16i16 (setcc (v16i16 LASX256:$xj), (v16i16 LASX256:$xk), CC)),
(!cast<LAInst>(Inst#"_HU") LASX256:$xj, LASX256:$xk)>;
def : Pat<(v8i32 (setcc (v8i32 LASX256:$xj), (v8i32 LASX256:$xk), CC)),
(!cast<LAInst>(Inst#"_WU") LASX256:$xj, LASX256:$xk)>;
def : Pat<(v4i64 (setcc (v4i64 LASX256:$xj), (v4i64 LASX256:$xk), CC)),
(!cast<LAInst>(Inst#"_DU") LASX256:$xj, LASX256:$xk)>;
}

multiclass PatCCXrXrF<CondCode CC, string Inst> {
def : Pat<(v8i32 (setcc (v8f32 LASX256:$xj), (v8f32 LASX256:$xk), CC)),
(!cast<LAInst>(Inst#"_S") LASX256:$xj, LASX256:$xk)>;
def : Pat<(v4i64 (setcc (v4f64 LASX256:$xj), (v4f64 LASX256:$xk), CC)),
(!cast<LAInst>(Inst#"_D") LASX256:$xj, LASX256:$xk)>;
}

let Predicates = [HasExtLASX] in {

// XVADD_{B/H/W/D}
Expand Down Expand Up @@ -1389,6 +1448,42 @@ def : Pat<(fma v8f32:$xj, v8f32:$xk, v8f32:$xa),
def : Pat<(fma v4f64:$xj, v4f64:$xk, v4f64:$xa),
(XVFMADD_D v4f64:$xj, v4f64:$xk, v4f64:$xa)>;

// XVSEQ[I]_{B/H/W/D}
defm : PatCCXrSimm5<SETEQ, "XVSEQI">;
defm : PatCCXrXr<SETEQ, "XVSEQ">;

// XVSLE[I]_{B/H/W/D}[U]
defm : PatCCXrSimm5<SETLE, "XVSLEI">;
defm : PatCCXrUimm5<SETULE, "XVSLEI">;
defm : PatCCXrXr<SETLE, "XVSLE">;
defm : PatCCXrXrU<SETULE, "XVSLE">;

// XVSLT[I]_{B/H/W/D}[U]
defm : PatCCXrSimm5<SETLT, "XVSLTI">;
defm : PatCCXrUimm5<SETULT, "XVSLTI">;
defm : PatCCXrXr<SETLT, "XVSLT">;
defm : PatCCXrXrU<SETULT, "XVSLT">;

// XVFCMP.cond.{S/D}
defm : PatCCXrXrF<SETEQ, "XVFCMP_CEQ">;
defm : PatCCXrXrF<SETOEQ, "XVFCMP_CEQ">;
defm : PatCCXrXrF<SETUEQ, "XVFCMP_CUEQ">;

defm : PatCCXrXrF<SETLE, "XVFCMP_CLE">;
defm : PatCCXrXrF<SETOLE, "XVFCMP_CLE">;
defm : PatCCXrXrF<SETULE, "XVFCMP_CULE">;

defm : PatCCXrXrF<SETLT, "XVFCMP_CLT">;
defm : PatCCXrXrF<SETOLT, "XVFCMP_CLT">;
defm : PatCCXrXrF<SETULT, "XVFCMP_CULT">;

defm : PatCCXrXrF<SETNE, "XVFCMP_CNE">;
defm : PatCCXrXrF<SETONE, "XVFCMP_CNE">;
defm : PatCCXrXrF<SETUNE, "XVFCMP_CUNE">;

defm : PatCCXrXrF<SETO, "XVFCMP_COR">;
defm : PatCCXrXrF<SETUO, "XVFCMP_CUN">;

// PseudoXVINSGR2VR_{B/H}
def : Pat<(vector_insert v32i8:$xd, GRLenVT:$rj, uimm5:$imm),
(PseudoXVINSGR2VR_B v32i8:$xd, GRLenVT:$rj, uimm5:$imm)>;
Expand Down
95 changes: 95 additions & 0 deletions llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1261,6 +1261,65 @@ multiclass PatShiftVrUimm<SDPatternOperator OpNode, string Inst> {
(!cast<LAInst>(Inst#"_D") LSX128:$vj, uimm6:$imm)>;
}

multiclass PatCCVrSimm5<CondCode CC, string Inst> {
def : Pat<(v16i8 (setcc (v16i8 LSX128:$vj),
(v16i8 (SplatPat_simm5 simm5:$imm)), CC)),
(!cast<LAInst>(Inst#"_B") LSX128:$vj, simm5:$imm)>;
def : Pat<(v8i16 (setcc (v8i16 LSX128:$vj),
(v8i16 (SplatPat_simm5 simm5:$imm)), CC)),
(!cast<LAInst>(Inst#"_H") LSX128:$vj, simm5:$imm)>;
def : Pat<(v4i32 (setcc (v4i32 LSX128:$vj),
(v4i32 (SplatPat_simm5 simm5:$imm)), CC)),
(!cast<LAInst>(Inst#"_W") LSX128:$vj, simm5:$imm)>;
def : Pat<(v2i64 (setcc (v2i64 LSX128:$vj),
(v2i64 (SplatPat_simm5 simm5:$imm)), CC)),
(!cast<LAInst>(Inst#"_D") LSX128:$vj, simm5:$imm)>;
}

multiclass PatCCVrUimm5<CondCode CC, string Inst> {
def : Pat<(v16i8 (setcc (v16i8 LSX128:$vj),
(v16i8 (SplatPat_uimm5 uimm5:$imm)), CC)),
(!cast<LAInst>(Inst#"_BU") LSX128:$vj, uimm5:$imm)>;
def : Pat<(v8i16 (setcc (v8i16 LSX128:$vj),
(v8i16 (SplatPat_uimm5 uimm5:$imm)), CC)),
(!cast<LAInst>(Inst#"_HU") LSX128:$vj, uimm5:$imm)>;
def : Pat<(v4i32 (setcc (v4i32 LSX128:$vj),
(v4i32 (SplatPat_uimm5 uimm5:$imm)), CC)),
(!cast<LAInst>(Inst#"_WU") LSX128:$vj, uimm5:$imm)>;
def : Pat<(v2i64 (setcc (v2i64 LSX128:$vj),
(v2i64 (SplatPat_uimm5 uimm5:$imm)), CC)),
(!cast<LAInst>(Inst#"_DU") LSX128:$vj, uimm5:$imm)>;
}

multiclass PatCCVrVr<CondCode CC, string Inst> {
def : Pat<(v16i8 (setcc (v16i8 LSX128:$vj), (v16i8 LSX128:$vk), CC)),
(!cast<LAInst>(Inst#"_B") LSX128:$vj, LSX128:$vk)>;
def : Pat<(v8i16 (setcc (v8i16 LSX128:$vj), (v8i16 LSX128:$vk), CC)),
(!cast<LAInst>(Inst#"_H") LSX128:$vj, LSX128:$vk)>;
def : Pat<(v4i32 (setcc (v4i32 LSX128:$vj), (v4i32 LSX128:$vk), CC)),
(!cast<LAInst>(Inst#"_W") LSX128:$vj, LSX128:$vk)>;
def : Pat<(v2i64 (setcc (v2i64 LSX128:$vj), (v2i64 LSX128:$vk), CC)),
(!cast<LAInst>(Inst#"_D") LSX128:$vj, LSX128:$vk)>;
}

multiclass PatCCVrVrU<CondCode CC, string Inst> {
def : Pat<(v16i8 (setcc (v16i8 LSX128:$vj), (v16i8 LSX128:$vk), CC)),
(!cast<LAInst>(Inst#"_BU") LSX128:$vj, LSX128:$vk)>;
def : Pat<(v8i16 (setcc (v8i16 LSX128:$vj), (v8i16 LSX128:$vk), CC)),
(!cast<LAInst>(Inst#"_HU") LSX128:$vj, LSX128:$vk)>;
def : Pat<(v4i32 (setcc (v4i32 LSX128:$vj), (v4i32 LSX128:$vk), CC)),
(!cast<LAInst>(Inst#"_WU") LSX128:$vj, LSX128:$vk)>;
def : Pat<(v2i64 (setcc (v2i64 LSX128:$vj), (v2i64 LSX128:$vk), CC)),
(!cast<LAInst>(Inst#"_DU") LSX128:$vj, LSX128:$vk)>;
}

multiclass PatCCVrVrF<CondCode CC, string Inst> {
def : Pat<(v4i32 (setcc (v4f32 LSX128:$vj), (v4f32 LSX128:$vk), CC)),
(!cast<LAInst>(Inst#"_S") LSX128:$vj, LSX128:$vk)>;
def : Pat<(v2i64 (setcc (v2f64 LSX128:$vj), (v2f64 LSX128:$vk), CC)),
(!cast<LAInst>(Inst#"_D") LSX128:$vj, LSX128:$vk)>;
}

let Predicates = [HasExtLSX] in {

// VADD_{B/H/W/D}
Expand Down Expand Up @@ -1466,6 +1525,42 @@ def : Pat<(fma v4f32:$vj, v4f32:$vk, v4f32:$va),
def : Pat<(fma v2f64:$vj, v2f64:$vk, v2f64:$va),
(VFMADD_D v2f64:$vj, v2f64:$vk, v2f64:$va)>;

// VSEQ[I]_{B/H/W/D}
defm : PatCCVrSimm5<SETEQ, "VSEQI">;
defm : PatCCVrVr<SETEQ, "VSEQ">;

// VSLE[I]_{B/H/W/D}[U]
defm : PatCCVrSimm5<SETLE, "VSLEI">;
defm : PatCCVrUimm5<SETULE, "VSLEI">;
defm : PatCCVrVr<SETLE, "VSLE">;
defm : PatCCVrVrU<SETULE, "VSLE">;

// VSLT[I]_{B/H/W/D}[U]
defm : PatCCVrSimm5<SETLT, "VSLTI">;
defm : PatCCVrUimm5<SETULT, "VSLTI">;
defm : PatCCVrVr<SETLT, "VSLT">;
defm : PatCCVrVrU<SETULT, "VSLT">;

// VFCMP.cond.{S/D}
defm : PatCCVrVrF<SETEQ, "VFCMP_CEQ">;
defm : PatCCVrVrF<SETOEQ, "VFCMP_CEQ">;
defm : PatCCVrVrF<SETUEQ, "VFCMP_CUEQ">;

defm : PatCCVrVrF<SETLE, "VFCMP_CLE">;
defm : PatCCVrVrF<SETOLE, "VFCMP_CLE">;
defm : PatCCVrVrF<SETULE, "VFCMP_CULE">;

defm : PatCCVrVrF<SETLT, "VFCMP_CLT">;
defm : PatCCVrVrF<SETOLT, "VFCMP_CLT">;
defm : PatCCVrVrF<SETULT, "VFCMP_CULT">;

defm : PatCCVrVrF<SETNE, "VFCMP_CNE">;
defm : PatCCVrVrF<SETONE, "VFCMP_CNE">;
defm : PatCCVrVrF<SETUNE, "VFCMP_CUNE">;

defm : PatCCVrVrF<SETO, "VFCMP_COR">;
defm : PatCCVrVrF<SETUO, "VFCMP_CUN">;

// VINSGR2VR_{B/H/W/D}
def : Pat<(vector_insert v16i8:$vd, GRLenVT:$rj, uimm4:$imm),
(VINSGR2VR_B v16i8:$vd, GRLenVT:$rj, uimm4:$imm)>;
Expand Down
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