-
Notifications
You must be signed in to change notification settings - Fork 10.9k
Commit
This commit does not belong to any branch on this repository, and may belong to a fork outside of the repository.
[PhaseOrdering] Add tests showing missed simplifications.
Add tests showing missed simplifications due to phase ordering.
- Loading branch information
Showing
2 changed files
with
180 additions
and
0 deletions.
There are no files selected for viewing
82 changes: 82 additions & 0 deletions
82
llvm/test/Transforms/PhaseOrdering/AArch64/extra-unroll-simplifications.ll
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,82 @@ | ||
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 | ||
; RUN: opt -passes='default<O3>' -S %s | FileCheck %s | ||
|
||
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" | ||
target triple = "arm64-apple-macosx11.0.0" | ||
|
||
define void @partial_unroll_forced(i32 %N, ptr %src, ptr noalias %dst) { | ||
; CHECK-LABEL: define void @partial_unroll_forced( | ||
; CHECK-SAME: i32 [[N:%.*]], ptr nocapture readonly [[SRC:%.*]], ptr noalias nocapture writeonly [[DST:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { | ||
; CHECK-NEXT: entry: | ||
; CHECK-NEXT: [[CMP141:%.*]] = icmp sgt i32 [[N]], 0 | ||
; CHECK-NEXT: br i1 [[CMP141]], label [[LOOP_LATCH_PREHEADER:%.*]], label [[EXIT:%.*]] | ||
; CHECK: loop.latch.preheader: | ||
; CHECK-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext nneg i32 [[N]] to i64 | ||
; CHECK-NEXT: [[XTRAITER:%.*]] = and i64 [[WIDE_TRIP_COUNT]], 1 | ||
; CHECK-NEXT: [[TMP0:%.*]] = icmp eq i32 [[N]], 1 | ||
; CHECK-NEXT: br i1 [[TMP0]], label [[EXIT_LOOPEXIT_UNR_LCSSA:%.*]], label [[LOOP_LATCH_PREHEADER_NEW:%.*]] | ||
; CHECK: loop.latch.preheader.new: | ||
; CHECK-NEXT: [[UNROLL_ITER:%.*]] = and i64 [[WIDE_TRIP_COUNT]], 2147483646 | ||
; CHECK-NEXT: br label [[LOOP_LATCH:%.*]] | ||
; CHECK: loop.latch: | ||
; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[LOOP_LATCH_PREHEADER_NEW]] ], [ [[INDVARS_IV_NEXT_1:%.*]], [[LOOP_LATCH]] ] | ||
; CHECK-NEXT: [[NITER:%.*]] = phi i64 [ 0, [[LOOP_LATCH_PREHEADER_NEW]] ], [ [[NITER_NEXT_1:%.*]], [[LOOP_LATCH]] ] | ||
; CHECK-NEXT: [[SRC_IDX:%.*]] = getelementptr <8 x half>, ptr [[SRC]], i64 [[INDVARS_IV]] | ||
; CHECK-NEXT: [[L:%.*]] = load <8 x half>, ptr [[SRC_IDX]], align 16 | ||
; CHECK-NEXT: [[DST_IDX:%.*]] = getelementptr <8 x half>, ptr [[DST]], i64 [[INDVARS_IV]] | ||
; CHECK-NEXT: [[ADD:%.*]] = fadd <8 x half> [[L]], [[L]] | ||
; CHECK-NEXT: store <8 x half> [[ADD]], ptr [[DST_IDX]], align 16 | ||
; CHECK-NEXT: [[INDVARS_IV_NEXT:%.*]] = or disjoint i64 [[INDVARS_IV]], 1 | ||
; CHECK-NEXT: [[SRC_IDX_1:%.*]] = getelementptr <8 x half>, ptr [[SRC]], i64 [[INDVARS_IV_NEXT]] | ||
; CHECK-NEXT: [[L_1:%.*]] = load <8 x half>, ptr [[SRC_IDX_1]], align 16 | ||
; CHECK-NEXT: [[DST_IDX_1:%.*]] = getelementptr <8 x half>, ptr [[DST]], i64 [[INDVARS_IV_NEXT]] | ||
; CHECK-NEXT: [[ADD_1:%.*]] = fadd <8 x half> [[L_1]], [[L_1]] | ||
; CHECK-NEXT: store <8 x half> [[ADD_1]], ptr [[DST_IDX_1]], align 16 | ||
; CHECK-NEXT: [[INDVARS_IV_NEXT_1]] = add nuw nsw i64 [[INDVARS_IV]], 2 | ||
; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2 | ||
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]] | ||
; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label [[EXIT_LOOPEXIT_UNR_LCSSA]], label [[LOOP_LATCH]], !llvm.loop [[LOOP0:![0-9]+]] | ||
; CHECK: exit.loopexit.unr-lcssa: | ||
; CHECK-NEXT: [[INDVARS_IV_UNR:%.*]] = phi i64 [ 0, [[LOOP_LATCH_PREHEADER]] ], [ [[INDVARS_IV_NEXT_1]], [[LOOP_LATCH]] ] | ||
; CHECK-NEXT: [[LCMP_MOD_NOT:%.*]] = icmp eq i64 [[XTRAITER]], 0 | ||
; CHECK-NEXT: br i1 [[LCMP_MOD_NOT]], label [[EXIT]], label [[LOOP_LATCH_EPIL:%.*]] | ||
; CHECK: loop.latch.epil: | ||
; CHECK-NEXT: [[SRC_IDX_EPIL:%.*]] = getelementptr <8 x half>, ptr [[SRC]], i64 [[INDVARS_IV_UNR]] | ||
; CHECK-NEXT: [[L_EPIL:%.*]] = load <8 x half>, ptr [[SRC_IDX_EPIL]], align 16 | ||
; CHECK-NEXT: [[DST_IDX_EPIL:%.*]] = getelementptr <8 x half>, ptr [[DST]], i64 [[INDVARS_IV_UNR]] | ||
; CHECK-NEXT: [[ADD_EPIL:%.*]] = fadd <8 x half> [[L_EPIL]], [[L_EPIL]] | ||
; CHECK-NEXT: store <8 x half> [[ADD_EPIL]], ptr [[DST_IDX_EPIL]], align 16 | ||
; CHECK-NEXT: br label [[EXIT]] | ||
; CHECK: exit: | ||
; CHECK-NEXT: ret void | ||
; | ||
entry: | ||
br label %loop.header | ||
|
||
loop.header: | ||
%iv = phi i32 [ 0, %entry ], [ %iv.next, %loop.latch ] | ||
%cmp14 = icmp slt i32 %iv, %N | ||
br i1 %cmp14, label %loop.latch, label %exit | ||
|
||
loop.latch: | ||
%iv.ext = zext i32 %iv to i64 | ||
%src.idx = getelementptr <8 x half>, ptr %src, i64 %iv.ext | ||
%l = load <8 x half>, ptr %src.idx, align 16 | ||
%dst.idx = getelementptr <8 x half>, ptr %dst, i64 %iv.ext | ||
%add = fadd <8 x half> %l, %l | ||
store <8 x half> %add, ptr %dst.idx, align 16 | ||
%iv.next = add i32 %iv, 1 | ||
br label %loop.header, !llvm.loop !0 | ||
|
||
exit: | ||
ret void | ||
} | ||
|
||
!0 = distinct !{!0, !1, !2} | ||
!1 = !{!"llvm.loop.mustprogress"} | ||
!2 = !{!"llvm.loop.unroll.count", i32 2} | ||
;. | ||
; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]} | ||
; CHECK: [[META1]] = !{!"llvm.loop.mustprogress"} | ||
; CHECK: [[META2]] = !{!"llvm.loop.unroll.disable"} | ||
;. |
98 changes: 98 additions & 0 deletions
98
llvm/test/Transforms/PhaseOrdering/AArch64/hoist-runtime-checks.ll
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,98 @@ | ||
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 | ||
; RUN: opt -passes='default<O3>' -S %s | FileCheck %s | ||
|
||
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" | ||
target triple = "arm64-apple-macosx11.0.0" | ||
|
||
define i32 @read_only_loop_with_runtime_check(ptr noundef %array, i32 noundef %count, i32 noundef %n) { | ||
; CHECK-LABEL: define i32 @read_only_loop_with_runtime_check( | ||
; CHECK-SAME: ptr nocapture noundef readonly [[ARRAY:%.*]], i32 noundef [[COUNT:%.*]], i32 noundef [[N:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { | ||
; CHECK-NEXT: entry: | ||
; CHECK-NEXT: [[CMP6_NOT:%.*]] = icmp eq i32 [[N]], 0 | ||
; CHECK-NEXT: br i1 [[CMP6_NOT]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_BODY_PREHEADER:%.*]] | ||
; CHECK: for.body.preheader: | ||
; CHECK-NEXT: [[TMP0:%.*]] = zext i32 [[N]] to i64 | ||
; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[N]], -1 | ||
; CHECK-NEXT: [[DOTNOT_NOT:%.*]] = icmp ult i32 [[TMP1]], [[COUNT]] | ||
; CHECK-NEXT: br label [[FOR_BODY:%.*]] | ||
; CHECK: for.cond.cleanup: | ||
; CHECK-NEXT: [[SUM_0_LCSSA:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[ADD:%.*]], [[IF_END:%.*]] ] | ||
; CHECK-NEXT: ret i32 [[SUM_0_LCSSA]] | ||
; CHECK: for.body: | ||
; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[FOR_BODY_PREHEADER]] ], [ [[INDVARS_IV_NEXT:%.*]], [[IF_END]] ] | ||
; CHECK-NEXT: [[SUM_07:%.*]] = phi i32 [ 0, [[FOR_BODY_PREHEADER]] ], [ [[ADD]], [[IF_END]] ] | ||
; CHECK-NEXT: br i1 [[DOTNOT_NOT]], label [[IF_END]], label [[IF_THEN:%.*]] | ||
; CHECK: if.then: | ||
; CHECK-NEXT: tail call void @llvm.trap() | ||
; CHECK-NEXT: unreachable | ||
; CHECK: if.end: | ||
; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[ARRAY]], i64 [[INDVARS_IV]] | ||
; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 | ||
; CHECK-NEXT: [[ADD]] = add nsw i32 [[TMP2]], [[SUM_07]] | ||
; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1 | ||
; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], [[TMP0]] | ||
; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY]] | ||
; | ||
entry: | ||
%array.addr = alloca ptr, align 8 | ||
%count.addr = alloca i32, align 4 | ||
%n.addr = alloca i32, align 4 | ||
%sum = alloca i32, align 4 | ||
%i = alloca i32, align 4 | ||
store ptr %array, ptr %array.addr, align 8 | ||
store i32 %count, ptr %count.addr, align 4 | ||
store i32 %n, ptr %n.addr, align 4 | ||
call void @llvm.lifetime.start.p0(i64 4, ptr %sum) #3 | ||
store i32 0, ptr %sum, align 4 | ||
call void @llvm.lifetime.start.p0(i64 4, ptr %i) #3 | ||
store i32 0, ptr %i, align 4 | ||
br label %for.cond | ||
|
||
for.cond: ; preds = %for.inc, %entry | ||
%0 = load i32, ptr %i, align 4 | ||
%1 = load i32, ptr %n.addr, align 4 | ||
%cmp = icmp ult i32 %0, %1 | ||
br i1 %cmp, label %for.body, label %for.cond.cleanup | ||
|
||
for.cond.cleanup: ; preds = %for.cond | ||
call void @llvm.lifetime.end.p0(i64 4, ptr %i) #3 | ||
br label %for.end | ||
|
||
for.body: ; preds = %for.cond | ||
%2 = load i32, ptr %i, align 4 | ||
%3 = load i32, ptr %count.addr, align 4 | ||
%cmp1 = icmp uge i32 %2, %3 | ||
br i1 %cmp1, label %if.then, label %if.end | ||
|
||
if.then: ; preds = %for.body | ||
call void @llvm.trap() | ||
br label %if.end | ||
|
||
if.end: ; preds = %if.then, %for.body | ||
%4 = load ptr, ptr %array.addr, align 8 | ||
%5 = load i32, ptr %i, align 4 | ||
%idxprom = zext i32 %5 to i64 | ||
%arrayidx = getelementptr inbounds i32, ptr %4, i64 %idxprom | ||
%6 = load i32, ptr %arrayidx, align 4 | ||
%7 = load i32, ptr %sum, align 4 | ||
%add = add nsw i32 %7, %6 | ||
store i32 %add, ptr %sum, align 4 | ||
br label %for.inc | ||
|
||
for.inc: ; preds = %if.end | ||
%8 = load i32, ptr %i, align 4 | ||
%inc = add i32 %8, 1 | ||
store i32 %inc, ptr %i, align 4 | ||
br label %for.cond | ||
|
||
for.end: ; preds = %for.cond.cleanup | ||
%9 = load i32, ptr %sum, align 4 | ||
call void @llvm.lifetime.end.p0(i64 4, ptr %sum) | ||
ret i32 %9 | ||
} | ||
|
||
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) | ||
|
||
declare void @llvm.trap() | ||
|
||
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) |