AMDGPU: Fix allowing immediates for tail call pseudo.

The pseudo was using SSrc_b64, so it allowed folding immediates into the destination operand for a tail call to null. However, this is not a valid operand for the s_setpc_b64 this will be lowered to. Avoids printing the operand as an invalid immediate. Avoids a regression when tail calls are enabled in GlobalISel (somehow tail calls to null get deleted in the DAG).
llvm · Mar 21, 2021 · a0f5aad · a0f5aad
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commit a0f5aad
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diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -479,7 +479,7 @@ def SI_CALL : SPseudoInstSI <
 
 // Tail call handling pseudo
 def SI_TCRETURN : SPseudoInstSI <(outs),
-  (ins SSrc_b64:$src0, unknown:$callee, i32imm:$fpdiff),
+  (ins SReg_64:$src0, unknown:$callee, i32imm:$fpdiff),
   [(AMDGPUtc_return i64:$src0, tglobaladdr:$callee, i32:$fpdiff)]> {
   let Size = 4;
   let isCall = 1;

diff --git a/llvm/test/MC/AMDGPU/sop1-err.s b/llvm/test/MC/AMDGPU/sop1-err.s
@@ -39,3 +39,6 @@ s_mov_b32 s103, 1
 
 s_mov_b64 s[102:103], -1
 // VI: error: register not available on this GPU
+
+s_setpc_b64 0
+// GCN: error: invalid operand for instruction