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[NVPTX] Don't flag StoreRetVal memory chain operands as ReadMem (PR32…
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…146)

This fixes 47 of the 75 NVPTX '-verify-machineinstrs with EXPENSIVE_CHECKS' errors in PR32146.

Differential Revision: https://reviews.llvm.org/D33147

llvm-svn: 302942
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RKSimon committed May 12, 2017
1 parent e941248 commit a1978aa
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Showing 4 changed files with 6 additions and 5 deletions.
4 changes: 3 additions & 1 deletion llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
Expand Up @@ -2578,7 +2578,9 @@ NVPTXTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
EVT TheStoreType = ExtendIntegerRetVal ? MVT::i32 : VTs[i];
Chain = DAG.getMemIntrinsicNode(Op, dl, DAG.getVTList(MVT::Other),
StoreOperands, TheStoreType,
MachinePointerInfo(), 1);
MachinePointerInfo(), /* Align */ 1,
/* Volatile */ false, /* ReadMem */ false,
/* WriteMem */ true, /* Size */ 0);
// Cleanup vector state.
StoreOperands.clear();
}
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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/NVPTX/ctlz.ll
@@ -1,4 +1,4 @@
; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
; RUN: llc < %s -march=nvptx -mcpu=sm_20 -verify-machineinstrs | FileCheck %s

target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"

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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/NVPTX/ctpop.ll
@@ -1,4 +1,4 @@
; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
; RUN: llc < %s -march=nvptx -mcpu=sm_20 -verify-machineinstrs | FileCheck %s

target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"

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3 changes: 1 addition & 2 deletions llvm/test/CodeGen/NVPTX/cttz.ll
@@ -1,5 +1,4 @@
; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s

; RUN: llc < %s -march=nvptx -mcpu=sm_20 -verify-machineinstrs | FileCheck %s

target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"

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