[RISCV] Improve check prefixes in B extension tests. NFC

-Add Z for the B extension subextensions.
-Don't mention I along with B or its sub extensions.

This is based on comments in D107817.

Differential Revision: https://reviews.llvm.org/D107992

llvm/test/CodeGen/RISCV/rv32zbb-intrinsic.ll

@@ -1,21 +1,21 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-b -verify-machineinstrs < %s \
-; RUN:   | FileCheck %s -check-prefix=RV32IB
+; RUN:   | FileCheck %s -check-prefix=RV32B
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb -verify-machineinstrs < %s \
-; RUN:   | FileCheck %s -check-prefix=RV32IBB
+; RUN:   | FileCheck %s -check-prefix=RV32ZBB
 
 declare i32 @llvm.riscv.orc.b.i32(i32)
 
 define i32 @orcb(i32 %a) nounwind {
-; RV32IB-LABEL: orcb:
-; RV32IB:       # %bb.0:
-; RV32IB-NEXT:    orc.b a0, a0
-; RV32IB-NEXT:    ret
+; RV32B-LABEL: orcb:
+; RV32B:       # %bb.0:
+; RV32B-NEXT:    orc.b a0, a0
+; RV32B-NEXT:    ret
 ;
-; RV32IBB-LABEL: orcb:
-; RV32IBB:       # %bb.0:
-; RV32IBB-NEXT:    orc.b a0, a0
-; RV32IBB-NEXT:    ret
+; RV32ZBB-LABEL: orcb:
+; RV32ZBB:       # %bb.0:
+; RV32ZBB-NEXT:    orc.b a0, a0
+; RV32ZBB-NEXT:    ret
   %tmp = call i32 @llvm.riscv.orc.b.i32(i32 %a)
  ret i32 %tmp
 }