[mips] Add COP0 register class and use it in M[FT]C0/DM[FT]C0.

Summary: Previously it (incorrectly) used GPR's. Patch by Simon Dardis. A couple small corrections by myself. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10567 llvm-svn: 240883
llvm · Jun 27, 2015 · a3134fa · a3134fa
1 parent 8c7e29d
commit a3134fa
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Showing 44 changed files with 234 additions and 36 deletions.
diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
@@ -502,11 +502,11 @@ class MipsOperand : public MCParsedAsmOperand {
     RegKind_CCR = 128,    /// CCR
     RegKind_HWRegs = 256, /// HWRegs
     RegKind_COP3 = 512,   /// COP3
-
+    RegKind_COP0 = 1024,  /// COP0
     /// Potentially any (e.g. $1)
     RegKind_Numeric = RegKind_GPR | RegKind_FGR | RegKind_FCC | RegKind_MSA128 |
                       RegKind_MSACtrl | RegKind_COP2 | RegKind_ACC |
-                      RegKind_CCR | RegKind_HWRegs | RegKind_COP3
+                      RegKind_CCR | RegKind_HWRegs | RegKind_COP3 | RegKind_COP0
   };
 
 private:
@@ -668,6 +668,14 @@ class MipsOperand : public MCParsedAsmOperand {
     return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
   }
 
+  /// Coerce the register to COP0 and return the real register for the
+  /// current target.
+  unsigned getCOP0Reg() const {
+    assert(isRegIdx() && (RegIdx.Kind & RegKind_COP0) && "Invalid access!");
+    unsigned ClassID = Mips::COP0RegClassID;
+    return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
+  }
+
   /// Coerce the register to COP2 and return the real register for the
   /// current target.
   unsigned getCOP2Reg() const {
@@ -809,6 +817,11 @@ class MipsOperand : public MCParsedAsmOperand {
     Inst.addOperand(MCOperand::createReg(getMSACtrlReg()));
   }
 
+  void addCOP0AsmRegOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 1 && "Invalid number of operands!");
+    Inst.addOperand(MCOperand::createReg(getCOP0Reg()));
+  }
+
   void addCOP2AsmRegOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     Inst.addOperand(MCOperand::createReg(getCOP2Reg()));
@@ -1184,6 +1197,9 @@ class MipsOperand : public MCParsedAsmOperand {
   bool isACCAsmReg() const {
     return isRegIdx() && RegIdx.Kind & RegKind_ACC && RegIdx.Index <= 3;
   }
+  bool isCOP0AsmReg() const {
+    return isRegIdx() && RegIdx.Kind & RegKind_COP0 && RegIdx.Index <= 31;
+  }
   bool isCOP2AsmReg() const {
     return isRegIdx() && RegIdx.Kind & RegKind_COP2 && RegIdx.Index <= 31;
   }

diff --git a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
@@ -178,6 +178,11 @@ static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
                                                uint64_t Address,
                                                const void *Decoder);
 
+static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst,
+                                            unsigned RegNo,
+                                            uint64_t Address,
+                                            const void *Decoder);
+
 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
                                             unsigned RegNo,
                                             uint64_t Address,
@@ -1564,6 +1569,18 @@ static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
   return MCDisassembler::Success;
 }
 
+static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst,
+                                            unsigned RegNo,
+                                            uint64_t Address,
+                                            const void *Decoder) {
+  if (RegNo > 31)
+    return MCDisassembler::Fail;
+
+  unsigned Reg = getReg(Decoder, Mips::COP0RegClassID, RegNo);
+  Inst.addOperand(MCOperand::createReg(Reg));
+  return MCDisassembler::Success;
+}
+
 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
                                             unsigned RegNo,
                                             uint64_t Address,

diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsOptionRecord.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsOptionRecord.cpp
@@ -79,6 +79,9 @@ void MipsRegInfoRecord::SetPhysRegUsed(unsigned Reg,
     if (GPR32RegClass->contains(CurrentSubReg) ||
         GPR64RegClass->contains(CurrentSubReg))
       ri_gprmask |= Value;
+    else if (COP0RegClass->contains(CurrentSubReg))
+      ri_cprmask[0] |= Value;
+    // MIPS COP1 is the FPU.
     else if (FGR32RegClass->contains(CurrentSubReg) ||
              FGR64RegClass->contains(CurrentSubReg) ||
              AFGR64RegClass->contains(CurrentSubReg) ||

diff --git a/llvm/lib/Target/Mips/Mips64InstrInfo.td b/llvm/lib/Target/Mips/Mips64InstrInfo.td
@@ -427,10 +427,10 @@ def DMTC2_OCTEON : MFC2OP<"dmtc2", GPR64Opnd>, MFC2OP_FM<0x12, 5>;
 
 /// Move between CPU and coprocessor registers
 let DecoderNamespace = "Mips64", Predicates = [HasMips64] in {
-def DMFC0 : MFC3OP<"dmfc0", GPR64Opnd>, MFC3OP_FM<0x10, 1>;
-def DMTC0 : MFC3OP<"dmtc0", GPR64Opnd>, MFC3OP_FM<0x10, 5>, ISA_MIPS3;
-def DMFC2 : MFC3OP<"dmfc2", GPR64Opnd>, MFC3OP_FM<0x12, 1>, ISA_MIPS3;
-def DMTC2 : MFC3OP<"dmtc2", GPR64Opnd>, MFC3OP_FM<0x12, 5>, ISA_MIPS3;
+def DMFC0 : MFC3OP<"dmfc0", GPR64Opnd, COP0Opnd>, MFC3OP_FM<0x10, 1>, ISA_MIPS3;
+def DMTC0 : MTC3OP<"dmtc0", COP0Opnd, GPR64Opnd>, MFC3OP_FM<0x10, 5>, ISA_MIPS3;
+def DMFC2 : MFC3OP<"dmfc2", GPR64Opnd, COP2Opnd>, MFC3OP_FM<0x12, 1>, ISA_MIPS3;
+def DMTC2 : MTC3OP<"dmtc2", COP2Opnd, GPR64Opnd>, MFC3OP_FM<0x12, 5>, ISA_MIPS3;
 }
 
 //===----------------------------------------------------------------------===//
@@ -613,10 +613,10 @@ def : MipsInstAlias<"dsrl $rd, $rt, $rs",
                     ISA_MIPS3;
 
 // Two operand (implicit 0 selector) versions:
-def : MipsInstAlias<"dmfc0 $rt, $rd", (DMFC0 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;
-def : MipsInstAlias<"dmtc0 $rt, $rd", (DMTC0 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;
-def : MipsInstAlias<"dmfc2 $rt, $rd", (DMFC2 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;
-def : MipsInstAlias<"dmtc2 $rt, $rd", (DMTC2 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;
+def : MipsInstAlias<"dmfc0 $rt, $rd", (DMFC0 GPR64Opnd:$rt, COP0Opnd:$rd, 0), 0>;
+def : MipsInstAlias<"dmtc0 $rt, $rd", (DMTC0 COP0Opnd:$rd, GPR64Opnd:$rt, 0), 0>;
+def : MipsInstAlias<"dmfc2 $rt, $rd", (DMFC2 GPR64Opnd:$rt, COP2Opnd:$rd, 0), 0>;
+def : MipsInstAlias<"dmtc2 $rt, $rd", (DMTC2 COP2Opnd:$rd, GPR64Opnd:$rt, 0), 0>;
 
 let Predicates = [HasMips64, HasCnMips] in {
 def : MipsInstAlias<"synciobdma", (SYNC 0x2), 0>;

diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td
@@ -1050,8 +1050,12 @@ class SCBase<string opstr, RegisterOperand RO> :
   let Constraints = "$rt = $dst";
 }
 
-class MFC3OP<string asmstr, RegisterOperand RO> :
-  InstSE<(outs RO:$rt, RO:$rd, uimm16:$sel), (ins),
+class MFC3OP<string asmstr, RegisterOperand RO, RegisterOperand RD> :
+  InstSE<(outs RO:$rt), (ins RD:$rd, uimm16:$sel),
+         !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>;
+
+class MTC3OP<string asmstr, RegisterOperand RO, RegisterOperand RD> :
+  InstSE<(outs RO:$rd), (ins RD:$rt, uimm16:$sel),
          !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>;
 
 class TrapBase<Instruction RealInst>
@@ -1488,10 +1492,10 @@ def EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>, EXT_FM<0>;
 def INS : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>, EXT_FM<4>;
 
 /// Move Control Registers From/To CPU Registers
-def MFC0 : MFC3OP<"mfc0", GPR32Opnd>, MFC3OP_FM<0x10, 0>, ISA_MIPS32;
-def MTC0 : MFC3OP<"mtc0", GPR32Opnd>, MFC3OP_FM<0x10, 4>, ISA_MIPS32;
-def MFC2 : MFC3OP<"mfc2", GPR32Opnd>, MFC3OP_FM<0x12, 0>;
-def MTC2 : MFC3OP<"mtc2", GPR32Opnd>, MFC3OP_FM<0x12, 4>;
+def MFC0 : MFC3OP<"mfc0", GPR32Opnd, COP0Opnd>, MFC3OP_FM<0x10, 0>, ISA_MIPS32;
+def MTC0 : MTC3OP<"mtc0", COP0Opnd, GPR32Opnd>, MFC3OP_FM<0x10, 4>, ISA_MIPS32;
+def MFC2 : MFC3OP<"mfc2", GPR32Opnd, COP2Opnd>, MFC3OP_FM<0x12, 0>;
+def MTC2 : MTC3OP<"mtc2", COP2Opnd, GPR32Opnd>, MFC3OP_FM<0x12, 4>;
 
 class Barrier<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
                                       FrmOther, asmstr>;
@@ -1608,10 +1612,10 @@ def : MipsInstAlias<"or $rs, $rt, $imm",
 def : MipsInstAlias<"or $rs, $imm",
                     (ORi GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>;
 def : MipsInstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
-def : MipsInstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
-def : MipsInstAlias<"mtc0 $rt, $rd", (MTC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
-def : MipsInstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
-def : MipsInstAlias<"mtc2 $rt, $rd", (MTC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
+def : MipsInstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, COP0Opnd:$rd, 0), 0>;
+def : MipsInstAlias<"mtc0 $rt, $rd", (MTC0 COP0Opnd:$rd, GPR32Opnd:$rt, 0), 0>;
+def : MipsInstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, COP2Opnd:$rd, 0), 0>;
+def : MipsInstAlias<"mtc2 $rt, $rd", (MTC2 COP2Opnd:$rd, GPR32Opnd:$rt, 0), 0>;
 let AdditionalPredicates = [NotInMicroMips] in {
 def : MipsInstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>;
 }

diff --git a/llvm/lib/Target/Mips/MipsOptionRecord.h b/llvm/lib/Target/Mips/MipsOptionRecord.h
@@ -49,6 +49,7 @@ class MipsRegInfoRecord : public MipsOptionRecord {
     FGR64RegClass = &(TRI->getRegClass(Mips::FGR64RegClassID));
     AFGR64RegClass = &(TRI->getRegClass(Mips::AFGR64RegClassID));
     MSA128BRegClass = &(TRI->getRegClass(Mips::MSA128BRegClassID));
+    COP0RegClass = &(TRI->getRegClass(Mips::COP0RegClassID));
     COP2RegClass = &(TRI->getRegClass(Mips::COP2RegClassID));
     COP3RegClass = &(TRI->getRegClass(Mips::COP3RegClassID));
   }
@@ -66,6 +67,7 @@ class MipsRegInfoRecord : public MipsOptionRecord {
   const MCRegisterClass *FGR64RegClass;
   const MCRegisterClass *AFGR64RegClass;
   const MCRegisterClass *MSA128BRegClass;
+  const MCRegisterClass *COP0RegClass;
   const MCRegisterClass *COP2RegClass;
   const MCRegisterClass *COP3RegClass;
   uint32_t ri_gprmask;

diff --git a/llvm/lib/Target/Mips/MipsRegisterInfo.td b/llvm/lib/Target/Mips/MipsRegisterInfo.td
@@ -201,6 +201,10 @@ let Namespace = "Mips" in {
   foreach I = 0-7 in
   def FCC#I : MipsReg<#I, "fcc"#I>;
 
+  // COP0 registers.
+  foreach I = 0-31 in
+  def COP0#I : MipsReg<#I, ""#I>;
+
   // COP2 registers.
   foreach I = 0-31 in
   def COP2#I : MipsReg<#I, ""#I>;
@@ -431,6 +435,10 @@ def ACC64DSP : RegisterClass<"Mips", [untyped], 64, (sequence "AC%u", 0, 3)> {
 
 def DSPCC : RegisterClass<"Mips", [v4i8, v2i16], 32, (add DSPCCond)>;
 
+// Coprocessor 0 registers.
+def COP0 : RegisterClass<"Mips", [i32], 32, (sequence "COP0%u", 0, 31)>,
+           Unallocatable;
+
 // Coprocessor 2 registers.
 def COP2 : RegisterClass<"Mips", [i32], 32, (sequence "COP2%u", 0, 31)>,
            Unallocatable;
@@ -559,6 +567,10 @@ def HWRegsAsmOperand : MipsAsmRegOperand {
   let Name = "HWRegsAsmReg";
 }
 
+def COP0AsmOperand : MipsAsmRegOperand {
+  let Name = "COP0AsmReg";
+}
+
 def COP2AsmOperand : MipsAsmRegOperand {
   let Name = "COP2AsmReg";
 }
@@ -609,6 +621,10 @@ def ACC64DSPOpnd : RegisterOperand<ACC64DSP> {
   let ParserMatchClass = ACC64DSPAsmOperand;
 }
 
+def COP0Opnd : RegisterOperand<COP0> {
+  let ParserMatchClass = COP0AsmOperand;
+}
+
 def COP2Opnd : RegisterOperand<COP2> {
   let ParserMatchClass = COP2AsmOperand;
 }

diff --git a/llvm/test/MC/Disassembler/Mips/mips32.txt b/llvm/test/MC/Disassembler/Mips/mips32.txt
@@ -255,6 +255,9 @@
 # CHECK: maddu  $6,  $7
 0x70 0xc7 0x00 0x01
 
+# CHECK: mfc0 $8, $16, 4
+0x40 0x08 0x80 0x04
+
 # CHECK: mfc1   $6, $f7
 0x44 0x06 0x38 0x00
 
@@ -294,6 +297,9 @@
 # CHECK: msubu  $6,  $7
 0x70 0xc7 0x00 0x05
 
+# CHECK: mtc0 $9, $15, 1
+0x40 0x89 0x78 0x01
+
 # CHECK: mtc1   $6, $f7
 0x44 0x86 0x38 0x00
 

diff --git a/llvm/test/MC/Disassembler/Mips/mips32/valid-mips32-el.txt b/llvm/test/MC/Disassembler/Mips/mips32/valid-mips32-el.txt
@@ -86,13 +86,15 @@
 0x10 0x00 0xa3 0x98 # CHECK: lwr $3, 16($5)
 0x00 0x00 0xc7 0x70 # CHECK: madd $6, $7
 0x01 0x00 0xc7 0x70 # CHECK: maddu $6, $7
+0x01 0x78 0x08 0x40 # CHECK: mfc0 $8, $15, 1
 0x00 0x38 0x06 0x44 # CHECK: mfc1 $6, $f7
 0x10 0x28 0x00 0x00 # CHECK: mfhi $5
 0x12 0x28 0x00 0x00 # CHECK: mflo $5
 0x86 0x41 0x20 0x46 # CHECK: mov.d $f6, $f8
 0x86 0x39 0x00 0x46 # CHECK: mov.s $f6, $f7
 0x04 0x00 0xc7 0x70 # CHECK: msub $6, $7
 0x05 0x00 0xc7 0x70 # CHECK: msubu $6, $7
+0x01 0x78 0x89 0x40 # CHECK: mtc0 $9, $15, 1
 0x00 0x38 0x86 0x44 # CHECK: mtc1 $6, $f7
 0x11 0x00 0xe0 0x00 # CHECK: mthi $7
 0x13 0x00 0xe0 0x00 # CHECK: mtlo $7

diff --git a/llvm/test/MC/Disassembler/Mips/mips32/valid-mips32.txt b/llvm/test/MC/Disassembler/Mips/mips32/valid-mips32.txt
@@ -86,13 +86,15 @@
 0x98 0xa3 0x00 0x10 # CHECK: lwr $3, 16($5)
 0x70 0xc7 0x00 0x00 # CHECK: madd $6, $7
 0x70 0xc7 0x00 0x01 # CHECK: maddu $6, $7
+0x40 0x08 0x78 0x01 # CHECK: mfc0 $8, $15, 1
 0x44 0x06 0x38 0x00 # CHECK: mfc1 $6, $f7
 0x00 0x00 0x28 0x10 # CHECK: mfhi $5
 0x00 0x00 0x28 0x12 # CHECK: mflo $5
 0x46 0x20 0x41 0x86 # CHECK: mov.d $f6, $f8
 0x46 0x00 0x39 0x86 # CHECK: mov.s $f6, $f7
 0x70 0xc7 0x00 0x04 # CHECK: msub $6, $7
 0x70 0xc7 0x00 0x05 # CHECK: msubu $6, $7
+0x40 0x89 0x78 0x01 # CHECK: mtc0 $9, $15, 1
 0x44 0x86 0x38 0x00 # CHECK: mtc1 $6, $f7
 0x00 0xe0 0x00 0x11 # CHECK: mthi $7
 0x00 0xe0 0x00 0x13 # CHECK: mtlo $7

diff --git a/llvm/test/MC/Disassembler/Mips/mips32_le.txt b/llvm/test/MC/Disassembler/Mips/mips32_le.txt
@@ -254,6 +254,9 @@
 # CHECK: maddu  $6,  $7
 0x01 0x00 0xc7 0x70
 
+# CHECK: mfc0 $8, $16, 4
+0x04 0x80 0x08 0x40
+
 # CHECK: mfc1   $6, $f7
 0x00 0x38 0x06 0x44
 
@@ -299,6 +302,9 @@
 # CHECK: msubu  $6,  $7
 0x05 0x00 0xc7 0x70
 
+# CHECK: mtc0 $9, $15, 1
+0x01 0x78 0x89 0x40
+
 # CHECK: mtc1   $6, $f7
 0x00 0x38 0x86 0x44
 

diff --git a/llvm/test/MC/Disassembler/Mips/mips32r2.txt b/llvm/test/MC/Disassembler/Mips/mips32r2.txt
@@ -269,6 +269,9 @@
 # CHECK: maddu  $6,  $7
 0x70 0xc7 0x00 0x01
 
+# CHECK: mfc0 $8, $16, 4
+0x40 0x08 0x80 0x04
+
 # CHECK: mfc1   $6, $f7
 0x44 0x06 0x38 0x00
 
@@ -290,6 +293,9 @@
 # CHECK: msubu  $6,  $7
 0x70 0xc7 0x00 0x05
 
+# CHECK: mtc0 $9, $15, 1
+0x40 0x89 0x78 0x01
+
 # CHECK: mtc1   $6, $f7
 0x44 0x86 0x38 0x00
 

diff --git a/llvm/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2-le.txt b/llvm/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2-le.txt
@@ -101,6 +101,7 @@
 0xa1 0xd4 0x94 0x4e # CHECK: madd.d $f18, $f20, $f26, $f20
 0x60 0x98 0xf9 0x4f # CHECK: madd.s $f1, $f31, $f19, $f25
 0x01 0x00 0xc7 0x70 # CHECK: maddu $6, $7
+0x01 0x78 0x08 0x40 # CHECK: mfc0 $8, $15, 1
 0x00 0x38 0x06 0x44 # CHECK: mfc1 $6, $f7
 0x10 0x28 0x00 0x00 # CHECK: mfhi $5
 0x00 0xc0 0x7e 0x44 # CHECK: mfhc1 $fp, $f24
@@ -111,6 +112,7 @@
 0xa9 0xf2 0x52 0x4c # CHECK: msub.d $f10, $f2, $f30, $f18
 0x28 0x53 0x70 0x4e # CHECK: msub.s $f12, $f19, $f10, $f16
 0x05 0x00 0xc7 0x70 # CHECK: msubu $6, $7
+0x01 0x78 0x89 0x40 # CHECK: mtc0 $9, $15, 1
 0x00 0x38 0x86 0x44 # CHECK: mtc1 $6, $f7
 0x11 0x00 0xe0 0x00 # CHECK: mthi $7
 0x00 0x80 0xe0 0x44 # CHECK: mthc1 $zero, $f16

diff --git a/llvm/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt b/llvm/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt
@@ -101,6 +101,7 @@
 0x4e 0x94 0xd4 0xa1 # CHECK: madd.d $f18, $f20, $f26, $f20
 0x4f 0xf9 0x98 0x60 # CHECK: madd.s $f1, $f31, $f19, $f25
 0x70 0xc7 0x00 0x01 # CHECK: maddu $6, $7
+0x40 0x08 0x78 0x01 # CHECK: mfc0 $8, $15, 1
 0x44 0x06 0x38 0x00 # CHECK: mfc1 $6, $f7
 0x00 0x00 0x28 0x10 # CHECK: mfhi $5
 0x44 0x7e 0xc0 0x00 # CHECK: mfhc1 $fp, $f24
@@ -111,6 +112,7 @@
 0x4c 0x52 0xf2 0xa9 # CHECK: msub.d $f10, $f2, $f30, $f18
 0x4e 0x70 0x53 0x28 # CHECK: msub.s $f12, $f19, $f10, $f16
 0x70 0xc7 0x00 0x05 # CHECK: msubu $6, $7
+0x40 0x89 0x78 0x01 # CHECK: mtc0 $9, $15, 1
 0x44 0x86 0x38 0x00 # CHECK: mtc1 $6, $f7
 0x00 0xe0 0x00 0x11 # CHECK: mthi $7
 0x44 0xe0 0x80 0x00 # CHECK: mthc1 $zero, $f16

diff --git a/llvm/test/MC/Disassembler/Mips/mips32r2_le.txt b/llvm/test/MC/Disassembler/Mips/mips32r2_le.txt
@@ -269,6 +269,9 @@
 # CHECK: maddu  $6,  $7
 0x01 0x00 0xc7 0x70
 
+# CHECK: mfc0 $8, $16, 4
+0x04 0x80 0x08 0x40
+
 # CHECK: mfc1   $6, $f7
 0x00 0x38 0x06 0x44
 
@@ -290,6 +293,9 @@
 # CHECK: msubu  $6,  $7
 0x05 0x00 0xc7 0x70
 
+# CHECK: mtc0 $9, $15, 1
+0x01 0x78 0x89 0x40
+
 # CHECK: mtc1   $6, $f7
 0x00 0x38 0x86 0x44
 

diff --git a/llvm/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3-le.txt b/llvm/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3-le.txt
@@ -98,6 +98,7 @@
 0xa1 0xd4 0x94 0x4e # CHECK: madd.d $f18, $f20, $f26, $f20
 0x60 0x98 0xf9 0x4f # CHECK: madd.s $f1, $f31, $f19, $f25
 0x01 0x00 0xc7 0x70 # CHECK: maddu $6, $7
+0x01 0x78 0x08 0x40 # CHECK: mfc0 $8, $15, 1
 0x00 0x38 0x06 0x44 # CHECK: mfc1 $6, $f7
 0x10 0x28 0x00 0x00 # CHECK: mfhi $5
 0x00 0xc0 0x7e 0x44 # CHECK: mfhc1 $fp, $f24
@@ -108,6 +109,7 @@
 0xa9 0xf2 0x52 0x4c # CHECK: msub.d $f10, $f2, $f30, $f18
 0x28 0x53 0x70 0x4e # CHECK: msub.s $f12, $f19, $f10, $f16
 0x05 0x00 0xc7 0x70 # CHECK: msubu $6, $7
+0x01 0x78 0x89 0x40 # CHECK: mtc0 $9, $15, 1
 0x00 0x38 0x86 0x44 # CHECK: mtc1 $6, $f7
 0x11 0x00 0xe0 0x00 # CHECK: mthi $7
 0x00 0x80 0xe0 0x44 # CHECK: mthc1 $zero, $f16