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[AArch64] Optimize floating point materialization
This patch follows some ideas from r352866 to optimize the floating point materialization even further. It changes isFPImmLegal to considere up to 2 mov instruction or up to 5 in case subtarget has fused literals. The rationale is the cost is the same for mov+fmov vs. adrp+ldr; but the mov+fmov sequence is always better because of the reduced d-cache pressure. The timings are still the same if you consider movw+movk+fmov vs. adrp+ldr will be fused (although one instruction longer). Reviewers: efriedma Differential Revision: https://reviews.llvm.org/D58460 llvm-svn: 356390
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Original file line number | Diff line number | Diff line change |
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; RUN: llc < %s -mtriple=arm64-apple-darwin | FileCheck %s | ||
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||
; CHECK: literal8 | ||
; CHECK: .quad 4614256656552045848 | ||
define double @foo() optsize { | ||
; CHECK: _foo: | ||
; CHECK: adrp x[[REG:[0-9]+]], lCPI0_0@PAGE | ||
; CHECK: ldr d0, [x[[REG]], lCPI0_0@PAGEOFF] | ||
; CHECK-NEXT: ret | ||
ret double 0x400921FB54442D18 | ||
} | ||
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; CHECK: literal8 | ||
; CHECK: .quad 137438953409 | ||
define double @foo2() optsize { | ||
; CHECK: _foo2: | ||
; CHECK: adrp x[[REG:[0-9]+]], lCPI1_0@PAGE | ||
; CHECK: ldr d0, [x[[REG]], lCPI1_0@PAGEOFF] | ||
; CHECK-NEXT: ret | ||
ret double 0x1FFFFFFFC1 | ||
} | ||
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||
define float @bar() optsize { | ||
; CHECK: _bar: | ||
; CHECK: adrp x[[REG:[0-9]+]], lCPI2_0@PAGE | ||
; CHECK: ldr s0, [x[[REG]], lCPI2_0@PAGEOFF] | ||
; CHECK-NEXT: ret | ||
ret float 0x400921FB60000000 | ||
} | ||
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||
; CHECK: literal16 | ||
; CHECK: .quad 0 | ||
; CHECK: .quad 0 | ||
define fp128 @baz() optsize { | ||
; CHECK: _baz: | ||
; CHECK: adrp x[[REG:[0-9]+]], lCPI3_0@PAGE | ||
; CHECK: ldr q0, [x[[REG]], lCPI3_0@PAGEOFF] | ||
; CHECK-NEXT: ret | ||
ret fp128 0xL00000000000000000000000000000000 | ||
} |
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