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[InstCombine] Support (mul (sext x), cst) --> (sext (mul x, cst')) an…
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…d (mul (zext x), cst) --> (zext (mul x, cst')) for vectors constants.

Similar to D51236, but for mul instead of add.

Differential Revision: https://reviews.llvm.org/D51900

llvm-svn: 341961
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@topperc
topperc committed Sep 11, 2018
1 parent 49d190f commit a57bb61
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Showing 2 changed files with 16 additions and 16 deletions.
4 changes: 2 additions & 2 deletions llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
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Expand Up @@ -327,7 +327,7 @@ Instruction *InstCombiner::visitMul(BinaryOperator &I) {
// integer mul followed by a sext.
if (SExtInst *Op0Conv = dyn_cast<SExtInst>(Op0)) {
// (mul (sext x), cst) --> (sext (mul x, cst'))
if (ConstantInt *Op1C = dyn_cast<ConstantInt>(Op1)) {
if (auto *Op1C = dyn_cast<Constant>(Op1)) {
if (Op0Conv->hasOneUse()) {
Constant *CI =
ConstantExpr::getTrunc(Op1C, Op0Conv->getOperand(0)->getType());
Expand Down Expand Up @@ -363,7 +363,7 @@ Instruction *InstCombiner::visitMul(BinaryOperator &I) {
// integer mul followed by a zext.
if (auto *Op0Conv = dyn_cast<ZExtInst>(Op0)) {
// (mul (zext x), cst) --> (zext (mul x, cst'))
if (ConstantInt *Op1C = dyn_cast<ConstantInt>(Op1)) {
if (auto *Op1C = dyn_cast<Constant>(Op1)) {
if (Op0Conv->hasOneUse()) {
Constant *CI =
ConstantExpr::getTrunc(Op1C, Op0Conv->getOperand(0)->getType());
Expand Down
28 changes: 14 additions & 14 deletions llvm/test/Transforms/InstCombine/sink-zext.ll
View file
Expand Up @@ -214,8 +214,8 @@ define i64 @test8(i32 %V) {
define <2 x i64> @test8_splat(<2 x i32> %V) {
; CHECK-LABEL: @test8_splat(
; CHECK-NEXT: [[ASHR:%.*]] = ashr <2 x i32> [[V:%.*]], <i32 16, i32 16>
; CHECK-NEXT: [[SEXT:%.*]] = sext <2 x i32> [[ASHR]] to <2 x i64>
; CHECK-NEXT: [[MUL:%.*]] = mul nsw <2 x i64> [[SEXT]], <i64 32767, i64 32767>
; CHECK-NEXT: [[MULCONV:%.*]] = mul nsw <2 x i32> [[ASHR]], <i32 32767, i32 32767>
; CHECK-NEXT: [[MUL:%.*]] = sext <2 x i32> [[MULCONV]] to <2 x i64>
; CHECK-NEXT: ret <2 x i64> [[MUL]]
;
%ashr = ashr <2 x i32> %V, <i32 16, i32 16>
Expand All @@ -227,8 +227,8 @@ define <2 x i64> @test8_splat(<2 x i32> %V) {
define <2 x i64> @test8_vec(<2 x i32> %V) {
; CHECK-LABEL: @test8_vec(
; CHECK-NEXT: [[ASHR:%.*]] = ashr <2 x i32> [[V:%.*]], <i32 16, i32 16>
; CHECK-NEXT: [[SEXT:%.*]] = sext <2 x i32> [[ASHR]] to <2 x i64>
; CHECK-NEXT: [[MUL:%.*]] = mul nsw <2 x i64> [[SEXT]], <i64 32767, i64 16384>
; CHECK-NEXT: [[MULCONV:%.*]] = mul nsw <2 x i32> [[ASHR]], <i32 32767, i32 16384>
; CHECK-NEXT: [[MUL:%.*]] = sext <2 x i32> [[MULCONV]] to <2 x i64>
; CHECK-NEXT: ret <2 x i64> [[MUL]]
;
%ashr = ashr <2 x i32> %V, <i32 16, i32 16>
Expand All @@ -240,8 +240,8 @@ define <2 x i64> @test8_vec(<2 x i32> %V) {
define <2 x i64> @test8_vec2(<2 x i32> %V) {
; CHECK-LABEL: @test8_vec2(
; CHECK-NEXT: [[ASHR:%.*]] = ashr <2 x i32> [[V:%.*]], <i32 16, i32 16>
; CHECK-NEXT: [[SEXT:%.*]] = sext <2 x i32> [[ASHR]] to <2 x i64>
; CHECK-NEXT: [[MUL:%.*]] = mul nsw <2 x i64> [[SEXT]], <i64 32767, i64 -32767>
; CHECK-NEXT: [[MULCONV:%.*]] = mul nsw <2 x i32> [[ASHR]], <i32 32767, i32 -32767>
; CHECK-NEXT: [[MUL:%.*]] = sext <2 x i32> [[MULCONV]] to <2 x i64>
; CHECK-NEXT: ret <2 x i64> [[MUL]]
;
%ashr = ashr <2 x i32> %V, <i32 16, i32 16>
Expand All @@ -266,8 +266,8 @@ define i64 @test9(i32 %V) {
define <2 x i64> @test9_splat(<2 x i32> %V) {
; CHECK-LABEL: @test9_splat(
; CHECK-NEXT: [[ASHR:%.*]] = ashr <2 x i32> [[V:%.*]], <i32 16, i32 16>
; CHECK-NEXT: [[SEXT:%.*]] = sext <2 x i32> [[ASHR]] to <2 x i64>
; CHECK-NEXT: [[MUL:%.*]] = mul nsw <2 x i64> [[SEXT]], <i64 -32767, i64 -32767>
; CHECK-NEXT: [[MULCONV:%.*]] = mul nsw <2 x i32> [[ASHR]], <i32 -32767, i32 -32767>
; CHECK-NEXT: [[MUL:%.*]] = sext <2 x i32> [[MULCONV]] to <2 x i64>
; CHECK-NEXT: ret <2 x i64> [[MUL]]
;
%ashr = ashr <2 x i32> %V, <i32 16, i32 16>
Expand All @@ -279,8 +279,8 @@ define <2 x i64> @test9_splat(<2 x i32> %V) {
define <2 x i64> @test9_vec(<2 x i32> %V) {
; CHECK-LABEL: @test9_vec(
; CHECK-NEXT: [[ASHR:%.*]] = ashr <2 x i32> [[V:%.*]], <i32 16, i32 16>
; CHECK-NEXT: [[SEXT:%.*]] = sext <2 x i32> [[ASHR]] to <2 x i64>
; CHECK-NEXT: [[MUL:%.*]] = mul nsw <2 x i64> [[SEXT]], <i64 -32767, i64 -10>
; CHECK-NEXT: [[MULCONV:%.*]] = mul nsw <2 x i32> [[ASHR]], <i32 -32767, i32 -10>
; CHECK-NEXT: [[MUL:%.*]] = sext <2 x i32> [[MULCONV]] to <2 x i64>
; CHECK-NEXT: ret <2 x i64> [[MUL]]
;
%ashr = ashr <2 x i32> %V, <i32 16, i32 16>
Expand All @@ -305,8 +305,8 @@ define i64 @test10(i32 %V) {
define <2 x i64> @test10_splat(<2 x i32> %V) {
; CHECK-LABEL: @test10_splat(
; CHECK-NEXT: [[LSHR:%.*]] = lshr <2 x i32> [[V:%.*]], <i32 16, i32 16>
; CHECK-NEXT: [[ZEXT:%.*]] = zext <2 x i32> [[LSHR]] to <2 x i64>
; CHECK-NEXT: [[MUL:%.*]] = mul nuw nsw <2 x i64> [[ZEXT]], <i64 65535, i64 65535>
; CHECK-NEXT: [[MULCONV:%.*]] = mul nuw <2 x i32> [[LSHR]], <i32 65535, i32 65535>
; CHECK-NEXT: [[MUL:%.*]] = zext <2 x i32> [[MULCONV]] to <2 x i64>
; CHECK-NEXT: ret <2 x i64> [[MUL]]
;
%lshr = lshr <2 x i32> %V, <i32 16, i32 16>
Expand All @@ -318,8 +318,8 @@ define <2 x i64> @test10_splat(<2 x i32> %V) {
define <2 x i64> @test10_vec(<2 x i32> %V) {
; CHECK-LABEL: @test10_vec(
; CHECK-NEXT: [[LSHR:%.*]] = lshr <2 x i32> [[V:%.*]], <i32 16, i32 16>
; CHECK-NEXT: [[ZEXT:%.*]] = zext <2 x i32> [[LSHR]] to <2 x i64>
; CHECK-NEXT: [[MUL:%.*]] = mul nuw nsw <2 x i64> [[ZEXT]], <i64 65535, i64 2>
; CHECK-NEXT: [[MULCONV:%.*]] = mul nuw <2 x i32> [[LSHR]], <i32 65535, i32 2>
; CHECK-NEXT: [[MUL:%.*]] = zext <2 x i32> [[MULCONV]] to <2 x i64>
; CHECK-NEXT: ret <2 x i64> [[MUL]]
;
%lshr = lshr <2 x i32> %V, <i32 16, i32 16>
Expand Down

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