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[clang][NFC] Bitfield access unit tests (#65742)
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Verify bitfield access units.
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@urnathan
urnathan committed Mar 29, 2024
1 parent 7344e99 commit a8ca4ab
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231 changes: 231 additions & 0 deletions clang/test/CodeGen/aapcs-bitfield-access-unit.c
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// RUN: %clang_cc1 -triple armv8-none-linux-eabi -fno-aapcs-bitfield-width -fdump-record-layouts-simple -emit-llvm -o /dev/null %s | FileCheck %s -check-prefixes=LAYOUT
// RUN: %clang_cc1 -triple armebv8-none-linux-eabi -fno-aapcs-bitfield-width -fdump-record-layouts-simple -emit-llvm -o /dev/null %s | FileCheck %s -check-prefixes=LAYOUT

// RUN: %clang_cc1 -triple armv8-none-linux-eabi -faapcs-bitfield-width -fdump-record-layouts-simple -emit-llvm -o /dev/null %s | FileCheck %s -check-prefixes=LAYOUT
// RUN: %clang_cc1 -triple armebv8-none-linux-eabi -faapcs-bitfield-width -fdump-record-layouts-simple -emit-llvm -o /dev/null %s | FileCheck %s -check-prefixes=LAYOUT

struct st0 {
short c : 7;
} st0;
// LAYOUT-LABEL: LLVMType:%struct.st0 =
// LAYOUT-SAME: type { i8, i8 }
// LAYOUT: BitFields:[
// LAYOUT-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:7 IsSigned:1 StorageSize:8 StorageOffset:0
// LAYOUT-NEXT: ]>

struct st1 {
int a : 10;
short c : 6;
} st1;
// LAYOUT-LABEL: LLVMType:%struct.st1 =
// LAYOUT-SAME: type { i16, [2 x i8] }
// LAYOUT: BitFields:[
// LAYOUT-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:10 IsSigned:1 StorageSize:16 StorageOffset:0
// LAYOUT-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:6 IsSigned:1 StorageSize:16 StorageOffset:0
// LAYOUT-NEXT: ]>

struct st2 {
int a : 10;
short c : 7;
} st2;
// LAYOUT-LABEL: LLVMType:%struct.st2 =
// LAYOUT-SAME: type { i16, i8 }
// LAYOUT: BitFields:[
// LAYOUT-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:10 IsSigned:1 StorageSize:16 StorageOffset:0
// LAYOUT-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:7 IsSigned:1 StorageSize:8 StorageOffset:2
// LAYOUT-NEXT: ]>

struct st3 {
volatile short c : 7;
} st3;
// LAYOUT-LABEL: LLVMType:%struct.st3 =
// LAYOUT-SAME: type { i8, i8 }
// LAYOUT: BitFields:[
// LAYOUT-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:7 IsSigned:1 StorageSize:8 StorageOffset:0
// LAYOUT-NEXT: ]>

struct st4 {
int b : 9;
volatile char c : 5;
} st4;
// LAYOUT-LABEL: LLVMType:%struct.st4 =
// LAYOUT-SAME: type { i16, [2 x i8] }
// LAYOUT: BitFields:[
// LAYOUT-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:9 IsSigned:1 StorageSize:16 StorageOffset:0
// LAYOUT-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:5 IsSigned:1 StorageSize:16 StorageOffset:0
// LAYOUT-NEXT: ]>

struct st5 {
int a : 12;
volatile char c : 5;
} st5;
// LAYOUT-LABEL: LLVMType:%struct.st5 =
// LAYOUT-SAME: type { i16, i8 }
// LAYOUT: BitFields:[
// LAYOUT-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:12 IsSigned:1 StorageSize:16 StorageOffset:0
// LAYOUT-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:5 IsSigned:1 StorageSize:8 StorageOffset:2
// LAYOUT-NEXT: ]>

struct st6 {
int a : 12;
char b;
int c : 5;
} st6;
// LAYOUT-LABEL: LLVMType:%struct.st6 =
// LAYOUT-SAME: type { i16, i8, i8 }
// LAYOUT: BitFields:[
// LAYOUT-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:12 IsSigned:1 StorageSize:16 StorageOffset:0
// LAYOUT-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:5 IsSigned:1 StorageSize:8 StorageOffset:3
// LAYOUT-NEXT: ]>

struct st7a {
char a;
int b : 5;
} st7a;
// LAYOUT-LABEL: LLVMType:%struct.st7a =
// LAYOUT-SAME: type { i8, i8, [2 x i8] }
// LAYOUT: BitFields:[
// LAYOUT-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:5 IsSigned:1 StorageSize:8 StorageOffset:1
// LAYOUT-NEXT: ]>

struct st7b {
char x;
volatile struct st7a y;
} st7b;
// LAYOUT-LABEL: LLVMType:%struct.st7b =
// LAYOUT-SAME: type { i8, [3 x i8], %struct.st7a }
// LAYOUT: BitFields:[
// LAYOUT-NEXT: ]>

struct st8 {
unsigned f : 16;
} st8;
// LAYOUT-LABEL: LLVMType:%struct.st8 =
// LAYOUT-SAME: type { i16, [2 x i8] }
// LAYOUT: BitFields:[
// LAYOUT-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:16 IsSigned:0 StorageSize:16 StorageOffset:0
// LAYOUT-NEXT: ]>

struct st9{
int f : 8;
} st9;
// LAYOUT-LABEL: LLVMType:%struct.st9 =
// LAYOUT-SAME: type { i8, [3 x i8] }
// LAYOUT: BitFields:[
// LAYOUT-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:8 IsSigned:1 StorageSize:8 StorageOffset:0
// LAYOUT-NEXT: ]>

struct st10{
int e : 1;
int f : 8;
} st10;
// LAYOUT-LABEL: LLVMType:%struct.st10 =
// LAYOUT-SAME: type { i16, [2 x i8] }
// LAYOUT: BitFields:[
// LAYOUT-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:1 IsSigned:1 StorageSize:16 StorageOffset:0
// LAYOUT-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:8 IsSigned:1 StorageSize:16 StorageOffset:0
// LAYOUT-NEXT: ]>

struct st11{
char e;
int f : 16;
} st11;
// LAYOUT-LABEL: LLVMType:%struct.st11 =
// LAYOUT-SAME: type <{ i8, i16, i8 }>
// LAYOUT: BitFields:[
// LAYOUT-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:16 IsSigned:1 StorageSize:16 StorageOffset:1
// LAYOUT-NEXT: ]>

struct st12{
int e : 8;
int f : 16;
} st12;
// LAYOUT-LABEL: LLVMType:%struct.st12 =
// LAYOUT-SAME: type { i24 }
// LAYOUT: BitFields:[
// LAYOUT-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:8 IsSigned:1 StorageSize:32 StorageOffset:0
// LAYOUT-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:16 IsSigned:1 StorageSize:32 StorageOffset:0
// LAYOUT-NEXT: ]>

struct st13 {
char a : 8;
int b : 32;
} __attribute__((packed)) st13;
// LAYOUT-LABEL: LLVMType:%struct.st13 =
// LAYOUT-SAME: type { [5 x i8] }
// LAYOUT: BitFields:[
// LAYOUT-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:8 IsSigned:1 StorageSize:40 StorageOffset:0
// LAYOUT-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:32 IsSigned:1 StorageSize:40 StorageOffset:0
// LAYOUT-NEXT: ]>

struct st14 {
char a : 8;
} __attribute__((packed)) st14;
// LAYOUT-LABEL: LLVMType:%struct.st14 =
// LAYOUT-SAME: type { i8 }
// LAYOUT: BitFields:[
// LAYOUT-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:8 IsSigned:1 StorageSize:8 StorageOffset:0
// LAYOUT-NEXT: ]>

struct st15 {
short a : 8;
} __attribute__((packed)) st15;
// LAYOUT-LABEL: LLVMType:%struct.st15 =
// LAYOUT-SAME: type { i8 }
// LAYOUT: BitFields:[
// LAYOUT-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:8 IsSigned:1 StorageSize:8 StorageOffset:0
// LAYOUT-NEXT: ]>

struct st16 {
int a : 32;
int b : 16;
int c : 32;
int d : 16;
} st16;
// LAYOUT-LABEL: LLVMType:%struct.st16 =
// LAYOUT-SAME: type { i48, i48 }
// LAYOUT: BitFields:[
// LAYOUT-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:32 IsSigned:1 StorageSize:64 StorageOffset:0
// LAYOUT-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:16 IsSigned:1 StorageSize:64 StorageOffset:0
// LAYOUT-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:32 IsSigned:1 StorageSize:64 StorageOffset:8
// LAYOUT-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:16 IsSigned:1 StorageSize:64 StorageOffset:8
// LAYOUT-NEXT: ]>

struct st17 {
int b : 32;
char c : 8;
} __attribute__((packed)) st17;
// LAYOUT-LABEL: LLVMType:%struct.st17 =
// LAYOUT-SAME: type { [5 x i8] }
// LAYOUT: BitFields:[
// LAYOUT-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:32 IsSigned:1 StorageSize:40 StorageOffset:0
// LAYOUT-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:8 IsSigned:1 StorageSize:40 StorageOffset:0
// LAYOUT-NEXT: ]>

struct zero_bitfield {
int a : 8;
char : 0;
int b : 8;
} st18;
// LAYOUT-LABEL: LLVMType:%struct.zero_bitfield =
// LAYOUT-SAME: type { i8, i8, [2 x i8] }
// LAYOUT: BitFields:[
// LAYOUT-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:8 IsSigned:1 StorageSize:8 StorageOffset:0
// LAYOUT-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:8 IsSigned:1 StorageSize:8 StorageOffset:1
// LAYOUT-NEXT: ]>

struct zero_bitfield_ok {
short a : 8;
char a1 : 8;
long : 0;
int b : 24;
} st19;
// LAYOUT-LABEL: LLVMType:%struct.zero_bitfield_ok =
// LAYOUT-SAME: type { i16, i24 }
// LAYOUT: BitFields:[
// LAYOUT-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:8 IsSigned:1 StorageSize:16 StorageOffset:0
// LAYOUT-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:8 IsSigned:1 StorageSize:16 StorageOffset:0
// LAYOUT-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:24 IsSigned:1 StorageSize:32 StorageOffset:4
// LAYOUT-NEXT: ]>


18 changes: 14 additions & 4 deletions clang/test/CodeGen/arm-bitfield-alignment.c
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Original file line number Diff line number Diff line change
@@ -1,5 +1,7 @@
// RUN: %clang_cc1 -triple arm-none-eabi -ffreestanding -emit-llvm -o - %s | FileCheck %s
// RUN: %clang_cc1 -triple aarch64 -ffreestanding -emit-llvm -o - %s | FileCheck %s
// RUN: %clang_cc1 -triple arm-none-eabi -fdump-record-layouts-simple -ffreestanding -emit-llvm -o %t %s | FileCheck %s -check-prefix=LAYOUT
// RUN: FileCheck %s -check-prefix=IR <%t
// RUN: %clang_cc1 -triple aarch64 -fdump-record-layouts-simple -ffreestanding -emit-llvm -o %t %s | FileCheck %s -check-prefix=LAYOUT
// RUN: FileCheck %s -check-prefix=IR <%t

extern struct T {
int b0 : 8;
Expand All @@ -11,5 +13,13 @@ int func(void) {
return g.b1;
}

// CHECK: @g = external global %struct.T, align 4
// CHECK: %{{.*}} = load i64, ptr @g, align 4
// IR: @g = external global %struct.T, align 4
// IR: %{{.*}} = load i64, ptr @g, align 4

// LAYOUT-LABEL: LLVMType:%struct.T =
// LAYOUT-SAME: type { i40 }
// LAYOUT: BitFields:[
// LAYOUT-NEXT: <CGBitFieldInfo Offset:0 Size:8 IsSigned:1 StorageSize:64 StorageOffset:0
// LAYOUT-NEXT: <CGBitFieldInfo Offset:8 Size:24 IsSigned:1 StorageSize:64 StorageOffset:0
// LAYOUT-NEXT: <CGBitFieldInfo Offset:32 Size:1 IsSigned:1 StorageSize:64 StorageOffset:0
// LAYOUT-NEXT: ]>
16 changes: 14 additions & 2 deletions clang/test/CodeGen/arm64-be-bitfield.c
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Original file line number Diff line number Diff line change
@@ -1,11 +1,23 @@
// RUN: %clang_cc1 -triple aarch64_be-linux-gnu -ffreestanding -emit-llvm -O0 -o - %s | FileCheck --check-prefix IR %s
// RUN: %clang_cc1 -triple aarch64_be-linux-gnu -ffreestanding -emit-llvm -O0 -o %t -fdump-record-layouts-simple %s | FileCheck %s --check-prefix=LAYOUT
// RUN: FileCheck %s --check-prefix=IR <%t

struct bt3 { signed b2:10; signed b3:10; } b16;

// Get the high 32-bits and then shift appropriately for big-endian.
signed callee_b0f(struct bt3 bp11) {
// IR: callee_b0f(i64 [[ARG:%.*]])
// IR: [[BP11:%.*]] = alloca %struct.bt3, align 4
// IR: store i64 [[ARG]], ptr [[PTR:%.*]], align 8
// IR: call void @llvm.memcpy.p0.p0.i64(ptr {{.*}}, ptr align 8 [[PTR]], i64 4
// IR: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[BP11]], ptr align 8 [[PTR]], i64 4
// IR: [[BF_LOAD:%.*]] = load i32, ptr [[BP11]], align 4
// IR: [[BF_ASHR:%.*]] = ashr i32 [[BF_LOAD]], 22
// IR: ret i32 [[BF_ASHR]]
return bp11.b2;
}

// LAYOUT-LABEL: LLVMType:%struct.bt3 =
// LAYOUT-SAME: type { i24 }
// LAYOUT: BitFields:[
// LAYOUT-NEXT: <CGBitFieldInfo Offset:22 Size:10 IsSigned:1 StorageSize:32 StorageOffset:0
// LAYOUT-NEXT: <CGBitFieldInfo Offset:12 Size:10 IsSigned:1 StorageSize:32 StorageOffset:0
// LAYOUT-NEXT: ]>

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