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[RISCV] Use __extendhfsf2/__truncsfhf2 for fp16 <-> fp32
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`__gnu_h2f_ieee` and `__gnu_f2h_ieee` are introduce by ARM and set that as
default name for fp16 and fp32 conversion in LLVM.

However RISC-V GCC using default naming scheme for that, which is
`__extendhfsf2` and `__truncsfhf2` for that, that cause runtime ABI
incompatible issue.

Although we didn't have formal runtime ABI spec to specify those naming
convention yet, but I think it would be great to fix the incompatible
issue first.

And I've plan to create a runtime ABI spec undere psABI spec this year.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D118207
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@kito-cheng
kito-cheng committed Jan 28, 2022
1 parent 7d17684 commit a9d5bb9
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Showing 10 changed files with 611 additions and 608 deletions.
3 changes: 3 additions & 0 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
View file
Expand Up @@ -1082,6 +1082,9 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setTargetDAGCombine(ISD::SHL);
setTargetDAGCombine(ISD::STORE);
}

setLibcallName(RTLIB::FPEXT_F16_F32, "__extendhfsf2");
setLibcallName(RTLIB::FPROUND_F32_F16, "__truncsfhf2");
}

EVT RISCVTargetLowering::getSetCCResultType(const DataLayout &DL,
Expand Down
48 changes: 24 additions & 24 deletions llvm/test/CodeGen/RISCV/calling-conv-half.ll
View file
Expand Up @@ -21,7 +21,7 @@ define i32 @callee_half_in_regs(i32 %a, half %b) nounwind {
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: slli a0, a1, 16
; RV32I-NEXT: srli a0, a0, 16
; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: call __extendhfsf2@plt
; RV32I-NEXT: call __fixsfsi@plt
; RV32I-NEXT: add a0, s0, a0
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
Expand All @@ -37,7 +37,7 @@ define i32 @callee_half_in_regs(i32 %a, half %b) nounwind {
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: slli a0, a1, 48
; RV64I-NEXT: srli a0, a0, 48
; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: call __extendhfsf2@plt
; RV64I-NEXT: call __fixsfdi@plt
; RV64I-NEXT: addw a0, s0, a0
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
Expand All @@ -52,7 +52,7 @@ define i32 @callee_half_in_regs(i32 %a, half %b) nounwind {
; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IF-NEXT: mv s0, a0
; RV32IF-NEXT: mv a0, a1
; RV32IF-NEXT: call __gnu_h2f_ieee@plt
; RV32IF-NEXT: call __extendhfsf2@plt
; RV32IF-NEXT: fmv.w.x ft0, a0
; RV32IF-NEXT: fcvt.w.s a0, ft0, rtz
; RV32IF-NEXT: add a0, s0, a0
Expand All @@ -68,7 +68,7 @@ define i32 @callee_half_in_regs(i32 %a, half %b) nounwind {
; RV64IF-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
; RV64IF-NEXT: mv s0, a0
; RV64IF-NEXT: mv a0, a1
; RV64IF-NEXT: call __gnu_h2f_ieee@plt
; RV64IF-NEXT: call __extendhfsf2@plt
; RV64IF-NEXT: fmv.w.x ft0, a0
; RV64IF-NEXT: fcvt.l.s a0, ft0, rtz
; RV64IF-NEXT: addw a0, s0, a0
Expand All @@ -84,7 +84,7 @@ define i32 @callee_half_in_regs(i32 %a, half %b) nounwind {
; RV32-ILP32F-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32-ILP32F-NEXT: mv s0, a0
; RV32-ILP32F-NEXT: fmv.x.w a0, fa0
; RV32-ILP32F-NEXT: call __gnu_h2f_ieee@plt
; RV32-ILP32F-NEXT: call __extendhfsf2@plt
; RV32-ILP32F-NEXT: fcvt.w.s a0, fa0, rtz
; RV32-ILP32F-NEXT: add a0, s0, a0
; RV32-ILP32F-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
Expand All @@ -99,7 +99,7 @@ define i32 @callee_half_in_regs(i32 %a, half %b) nounwind {
; RV64-LP64F-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
; RV64-LP64F-NEXT: mv s0, a0
; RV64-LP64F-NEXT: fmv.x.w a0, fa0
; RV64-LP64F-NEXT: call __gnu_h2f_ieee@plt
; RV64-LP64F-NEXT: call __extendhfsf2@plt
; RV64-LP64F-NEXT: fcvt.l.s a0, fa0, rtz
; RV64-LP64F-NEXT: addw a0, s0, a0
; RV64-LP64F-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
Expand All @@ -114,7 +114,7 @@ define i32 @callee_half_in_regs(i32 %a, half %b) nounwind {
; RV32-ILP32ZFHMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32-ILP32ZFHMIN-NEXT: mv s0, a0
; RV32-ILP32ZFHMIN-NEXT: fmv.x.w a0, fa0
; RV32-ILP32ZFHMIN-NEXT: call __gnu_h2f_ieee@plt
; RV32-ILP32ZFHMIN-NEXT: call __extendhfsf2@plt
; RV32-ILP32ZFHMIN-NEXT: fcvt.w.s a0, fa0, rtz
; RV32-ILP32ZFHMIN-NEXT: add a0, s0, a0
; RV32-ILP32ZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
Expand All @@ -129,7 +129,7 @@ define i32 @callee_half_in_regs(i32 %a, half %b) nounwind {
; RV64-LP64ZFHMIN-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
; RV64-LP64ZFHMIN-NEXT: mv s0, a0
; RV64-LP64ZFHMIN-NEXT: fmv.x.w a0, fa0
; RV64-LP64ZFHMIN-NEXT: call __gnu_h2f_ieee@plt
; RV64-LP64ZFHMIN-NEXT: call __extendhfsf2@plt
; RV64-LP64ZFHMIN-NEXT: fcvt.l.s a0, fa0, rtz
; RV64-LP64ZFHMIN-NEXT: addw a0, s0, a0
; RV64-LP64ZFHMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
Expand Down Expand Up @@ -247,7 +247,7 @@ define i32 @callee_half_on_stack(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f,
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: lhu a0, 16(sp)
; RV32I-NEXT: mv s0, a7
; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: call __extendhfsf2@plt
; RV32I-NEXT: call __fixsfsi@plt
; RV32I-NEXT: add a0, s0, a0
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
Expand All @@ -262,7 +262,7 @@ define i32 @callee_half_on_stack(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f,
; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: lhu a0, 16(sp)
; RV64I-NEXT: mv s0, a7
; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: call __extendhfsf2@plt
; RV64I-NEXT: call __fixsfdi@plt
; RV64I-NEXT: addw a0, s0, a0
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
Expand All @@ -277,7 +277,7 @@ define i32 @callee_half_on_stack(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f,
; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IF-NEXT: lhu a0, 16(sp)
; RV32IF-NEXT: mv s0, a7
; RV32IF-NEXT: call __gnu_h2f_ieee@plt
; RV32IF-NEXT: call __extendhfsf2@plt
; RV32IF-NEXT: fmv.w.x ft0, a0
; RV32IF-NEXT: fcvt.w.s a0, ft0, rtz
; RV32IF-NEXT: add a0, s0, a0
Expand All @@ -293,7 +293,7 @@ define i32 @callee_half_on_stack(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f,
; RV64IF-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
; RV64IF-NEXT: lhu a0, 16(sp)
; RV64IF-NEXT: mv s0, a7
; RV64IF-NEXT: call __gnu_h2f_ieee@plt
; RV64IF-NEXT: call __extendhfsf2@plt
; RV64IF-NEXT: fmv.w.x ft0, a0
; RV64IF-NEXT: fcvt.l.s a0, ft0, rtz
; RV64IF-NEXT: addw a0, s0, a0
Expand All @@ -309,7 +309,7 @@ define i32 @callee_half_on_stack(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f,
; RV32-ILP32F-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32-ILP32F-NEXT: mv s0, a7
; RV32-ILP32F-NEXT: fmv.x.w a0, fa0
; RV32-ILP32F-NEXT: call __gnu_h2f_ieee@plt
; RV32-ILP32F-NEXT: call __extendhfsf2@plt
; RV32-ILP32F-NEXT: fcvt.w.s a0, fa0, rtz
; RV32-ILP32F-NEXT: add a0, s0, a0
; RV32-ILP32F-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
Expand All @@ -324,7 +324,7 @@ define i32 @callee_half_on_stack(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f,
; RV64-LP64F-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
; RV64-LP64F-NEXT: mv s0, a7
; RV64-LP64F-NEXT: fmv.x.w a0, fa0
; RV64-LP64F-NEXT: call __gnu_h2f_ieee@plt
; RV64-LP64F-NEXT: call __extendhfsf2@plt
; RV64-LP64F-NEXT: fcvt.l.s a0, fa0, rtz
; RV64-LP64F-NEXT: addw a0, s0, a0
; RV64-LP64F-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
Expand All @@ -339,7 +339,7 @@ define i32 @callee_half_on_stack(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f,
; RV32-ILP32ZFHMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32-ILP32ZFHMIN-NEXT: mv s0, a7
; RV32-ILP32ZFHMIN-NEXT: fmv.x.w a0, fa0
; RV32-ILP32ZFHMIN-NEXT: call __gnu_h2f_ieee@plt
; RV32-ILP32ZFHMIN-NEXT: call __extendhfsf2@plt
; RV32-ILP32ZFHMIN-NEXT: fcvt.w.s a0, fa0, rtz
; RV32-ILP32ZFHMIN-NEXT: add a0, s0, a0
; RV32-ILP32ZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
Expand All @@ -354,7 +354,7 @@ define i32 @callee_half_on_stack(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f,
; RV64-LP64ZFHMIN-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
; RV64-LP64ZFHMIN-NEXT: mv s0, a7
; RV64-LP64ZFHMIN-NEXT: fmv.x.w a0, fa0
; RV64-LP64ZFHMIN-NEXT: call __gnu_h2f_ieee@plt
; RV64-LP64ZFHMIN-NEXT: call __extendhfsf2@plt
; RV64-LP64ZFHMIN-NEXT: fcvt.l.s a0, fa0, rtz
; RV64-LP64ZFHMIN-NEXT: addw a0, s0, a0
; RV64-LP64ZFHMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
Expand Down Expand Up @@ -586,7 +586,7 @@ define i32 @caller_half_ret() nounwind {
; RV32I-NEXT: call callee_half_ret@plt
; RV32I-NEXT: slli a0, a0, 16
; RV32I-NEXT: srli a0, a0, 16
; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: call __extendhfsf2@plt
; RV32I-NEXT: call __fixsfsi@plt
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
Expand All @@ -599,7 +599,7 @@ define i32 @caller_half_ret() nounwind {
; RV64I-NEXT: call callee_half_ret@plt
; RV64I-NEXT: slli a0, a0, 48
; RV64I-NEXT: srli a0, a0, 48
; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: call __extendhfsf2@plt
; RV64I-NEXT: call __fixsfdi@plt
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
Expand All @@ -610,7 +610,7 @@ define i32 @caller_half_ret() nounwind {
; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: call callee_half_ret@plt
; RV32IF-NEXT: call __gnu_h2f_ieee@plt
; RV32IF-NEXT: call __extendhfsf2@plt
; RV32IF-NEXT: fmv.w.x ft0, a0
; RV32IF-NEXT: fcvt.w.s a0, ft0, rtz
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
Expand All @@ -622,7 +622,7 @@ define i32 @caller_half_ret() nounwind {
; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: call callee_half_ret@plt
; RV64IF-NEXT: call __gnu_h2f_ieee@plt
; RV64IF-NEXT: call __extendhfsf2@plt
; RV64IF-NEXT: fmv.w.x ft0, a0
; RV64IF-NEXT: fcvt.l.s a0, ft0, rtz
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
Expand All @@ -635,7 +635,7 @@ define i32 @caller_half_ret() nounwind {
; RV32-ILP32F-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32-ILP32F-NEXT: call callee_half_ret@plt
; RV32-ILP32F-NEXT: fmv.x.w a0, fa0
; RV32-ILP32F-NEXT: call __gnu_h2f_ieee@plt
; RV32-ILP32F-NEXT: call __extendhfsf2@plt
; RV32-ILP32F-NEXT: fcvt.w.s a0, fa0, rtz
; RV32-ILP32F-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-ILP32F-NEXT: addi sp, sp, 16
Expand All @@ -647,7 +647,7 @@ define i32 @caller_half_ret() nounwind {
; RV64-LP64F-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64-LP64F-NEXT: call callee_half_ret@plt
; RV64-LP64F-NEXT: fmv.x.w a0, fa0
; RV64-LP64F-NEXT: call __gnu_h2f_ieee@plt
; RV64-LP64F-NEXT: call __extendhfsf2@plt
; RV64-LP64F-NEXT: fcvt.l.s a0, fa0, rtz
; RV64-LP64F-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64-LP64F-NEXT: addi sp, sp, 16
Expand All @@ -659,7 +659,7 @@ define i32 @caller_half_ret() nounwind {
; RV32-ILP32ZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32-ILP32ZFHMIN-NEXT: call callee_half_ret@plt
; RV32-ILP32ZFHMIN-NEXT: fmv.x.w a0, fa0
; RV32-ILP32ZFHMIN-NEXT: call __gnu_h2f_ieee@plt
; RV32-ILP32ZFHMIN-NEXT: call __extendhfsf2@plt
; RV32-ILP32ZFHMIN-NEXT: fcvt.w.s a0, fa0, rtz
; RV32-ILP32ZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-ILP32ZFHMIN-NEXT: addi sp, sp, 16
Expand All @@ -671,7 +671,7 @@ define i32 @caller_half_ret() nounwind {
; RV64-LP64ZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64-LP64ZFHMIN-NEXT: call callee_half_ret@plt
; RV64-LP64ZFHMIN-NEXT: fmv.x.w a0, fa0
; RV64-LP64ZFHMIN-NEXT: call __gnu_h2f_ieee@plt
; RV64-LP64ZFHMIN-NEXT: call __extendhfsf2@plt
; RV64-LP64ZFHMIN-NEXT: fcvt.l.s a0, fa0, rtz
; RV64-LP64ZFHMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64-LP64ZFHMIN-NEXT: addi sp, sp, 16
Expand Down
10 changes: 5 additions & 5 deletions llvm/test/CodeGen/RISCV/copysign-casts.ll
View file
Expand Up @@ -133,7 +133,7 @@ define double @fold_promote_d_h(double %a, half %b) nounwind {
; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: fmv.d fs0, fa0
; RV32IFD-NEXT: fmv.x.w a0, fa1
; RV32IFD-NEXT: call __gnu_h2f_ieee@plt
; RV32IFD-NEXT: call __extendhfsf2@plt
; RV32IFD-NEXT: fcvt.d.s ft0, fa0
; RV32IFD-NEXT: fsgnj.d fa0, fs0, ft0
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
Expand All @@ -148,7 +148,7 @@ define double @fold_promote_d_h(double %a, half %b) nounwind {
; RV64IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: fmv.d fs0, fa0
; RV64IFD-NEXT: fmv.x.w a0, fa1
; RV64IFD-NEXT: call __gnu_h2f_ieee@plt
; RV64IFD-NEXT: call __extendhfsf2@plt
; RV64IFD-NEXT: fcvt.d.s ft0, fa0
; RV64IFD-NEXT: fsgnj.d fa0, fs0, ft0
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
Expand Down Expand Up @@ -211,7 +211,7 @@ define float @fold_promote_f_h(float %a, half %b) nounwind {
; RV32IF-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fmv.s fs0, fa0
; RV32IF-NEXT: fmv.x.w a0, fa1
; RV32IF-NEXT: call __gnu_h2f_ieee@plt
; RV32IF-NEXT: call __extendhfsf2@plt
; RV32IF-NEXT: fsgnj.s fa0, fs0, fa0
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload
Expand All @@ -225,7 +225,7 @@ define float @fold_promote_f_h(float %a, half %b) nounwind {
; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: fmv.s fs0, fa0
; RV32IFD-NEXT: fmv.x.w a0, fa1
; RV32IFD-NEXT: call __gnu_h2f_ieee@plt
; RV32IFD-NEXT: call __extendhfsf2@plt
; RV32IFD-NEXT: fsgnj.s fa0, fs0, fa0
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload
Expand All @@ -239,7 +239,7 @@ define float @fold_promote_f_h(float %a, half %b) nounwind {
; RV64IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: fmv.s fs0, fa0
; RV64IFD-NEXT: fmv.x.w a0, fa1
; RV64IFD-NEXT: call __gnu_h2f_ieee@plt
; RV64IFD-NEXT: call __extendhfsf2@plt
; RV64IFD-NEXT: fsgnj.s fa0, fs0, fa0
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload
Expand Down
18 changes: 9 additions & 9 deletions llvm/test/CodeGen/RISCV/fp16-promote.ll
View file
Expand Up @@ -18,7 +18,7 @@ define float @test_fpextend_float(half* %p) nounwind {
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; CHECK-NEXT: lhu a0, 0(a0)
; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: call __extendhfsf2@plt
; CHECK-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
Expand All @@ -33,7 +33,7 @@ define double @test_fpextend_double(half* %p) nounwind {
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; CHECK-NEXT: lhu a0, 0(a0)
; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: call __extendhfsf2@plt
; CHECK-NEXT: fcvt.d.s fa0, fa0
; CHECK-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 16
Expand All @@ -50,7 +50,7 @@ define void @test_fptrunc_float(float %f, half* %p) nounwind {
; CHECK-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; CHECK-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; CHECK-NEXT: mv s0, a0
; CHECK-NEXT: call __gnu_f2h_ieee@plt
; CHECK-NEXT: call __truncsfhf2@plt
; CHECK-NEXT: sh a0, 0(s0)
; CHECK-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; CHECK-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
Expand Down Expand Up @@ -90,12 +90,12 @@ define void @test_fadd(half* %p, half* %q) nounwind {
; CHECK-NEXT: mv s0, a0
; CHECK-NEXT: lhu s1, 0(a0)
; CHECK-NEXT: lhu a0, 0(a1)
; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: call __extendhfsf2@plt
; CHECK-NEXT: fmv.s fs0, fa0
; CHECK-NEXT: mv a0, s1
; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: call __extendhfsf2@plt
; CHECK-NEXT: fadd.s fa0, fa0, fs0
; CHECK-NEXT: call __gnu_f2h_ieee@plt
; CHECK-NEXT: call __truncsfhf2@plt
; CHECK-NEXT: sh a0, 0(s0)
; CHECK-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; CHECK-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
Expand All @@ -121,12 +121,12 @@ define void @test_fmul(half* %p, half* %q) nounwind {
; CHECK-NEXT: mv s0, a0
; CHECK-NEXT: lhu s1, 0(a0)
; CHECK-NEXT: lhu a0, 0(a1)
; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: call __extendhfsf2@plt
; CHECK-NEXT: fmv.s fs0, fa0
; CHECK-NEXT: mv a0, s1
; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: call __extendhfsf2@plt
; CHECK-NEXT: fmul.s fa0, fa0, fs0
; CHECK-NEXT: call __gnu_f2h_ieee@plt
; CHECK-NEXT: call __truncsfhf2@plt
; CHECK-NEXT: sh a0, 0(s0)
; CHECK-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; CHECK-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
Expand Down

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