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[DAGCombine] Moved X86 rotate_amount % bitwidth == 0 early out to DAG…
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…Combiner

Remove common code from custom lowering (code is still safe if somehow a zero value gets used).

llvm-svn: 349028
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RKSimon committed Dec 13, 2018
1 parent 1a4e2cc commit ab973a4
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Showing 2 changed files with 8 additions and 8 deletions.
7 changes: 7 additions & 0 deletions llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Expand Up @@ -6314,6 +6314,13 @@ SDValue DAGCombiner::visitRotate(SDNode *N) {
if (isNullOrNullSplat(N1))
return N0;

// fold (rot x, c) -> x iff (c % BitSize) == 0
if (isPowerOf2_32(Bitsize) && Bitsize > 1) {
APInt ModuloMask(N1.getScalarValueSizeInBits(), Bitsize - 1);
if (DAG.MaskedValueIsZero(N1, ModuloMask))
return N0;
}

// fold (rot x, c) -> (rot x, c % BitSize)
if (ConstantSDNode *Cst = isConstOrConstSplat(N1)) {
if (Cst->getAPIntValue().uge(Bitsize)) {
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9 changes: 1 addition & 8 deletions llvm/lib/Target/X86/X86ISelLowering.cpp
Expand Up @@ -24793,9 +24793,6 @@ static SDValue LowerRotate(SDValue Op, const X86Subtarget &Subtarget,
if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
if (auto *RotateConst = BVAmt->getConstantSplatNode()) {
uint64_t RotateAmt = RotateConst->getAPIntValue().urem(EltSizeInBits);
if (RotateAmt == 0)
return R;

return DAG.getNode(X86ISD::VROTLI, DL, VT, R,
DAG.getConstant(RotateAmt, DL, MVT::i8));
}
Expand All @@ -24816,12 +24813,8 @@ static SDValue LowerRotate(SDValue Op, const X86Subtarget &Subtarget,

// Rotate by an uniform constant - expand back to shifts.
if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt))
if (auto *RotateConst = BVAmt->getConstantSplatNode()) {
uint64_t RotateAmt = RotateConst->getAPIntValue().urem(EltSizeInBits);
if (RotateAmt == 0)
return R;
if (BVAmt->getConstantSplatNode())
return SDValue();
}

// TODO: ISD::ROT* uses modulo rotate amounts, we need to handle this.

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