[InstCombine] Fix incorrect nneg inference on shift amount

Whether this is valid depends on the bit widths of the involved integers. Fixes #72927.
llvm · Nov 21, 2023 · ac75171 · ac75171
1 parent a1652fd
commit ac75171
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Showing 2 changed files with 5 additions and 3 deletions.
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp b/llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
@@ -1223,7 +1223,9 @@ Instruction *InstCombinerImpl::visitZExt(ZExtInst &Zext) {
 
   if (!Zext.hasNonNeg()) {
     // If this zero extend is only used by a shift, add nneg flag.
-    if (Zext.hasOneUse() && SrcTy->getScalarSizeInBits() > 2 &&
+    if (Zext.hasOneUse() &&
+        SrcTy->getScalarSizeInBits() >
+            Log2_64_Ceil(DestTy->getScalarSizeInBits()) &&
         match(Zext.user_back(), m_Shift(m_Value(), m_Specific(&Zext)))) {
       Zext.setNonNeg();
       return &Zext;

diff --git a/llvm/test/Transforms/InstCombine/shift.ll b/llvm/test/Transforms/InstCombine/shift.ll
@@ -2208,8 +2208,8 @@ define i128 @shift_zext_nneg(i8 %arg) {
 
 define i129 @shift_zext_not_nneg(i8 %arg) {
 ; CHECK-LABEL: @shift_zext_not_nneg(
-; CHECK-NEXT:    [[EXT:%.*]] = zext nneg i8 [[ARG:%.*]] to i129
-; CHECK-NEXT:    [[SHL:%.*]] = shl nuw nsw i129 1, [[EXT]]
+; CHECK-NEXT:    [[EXT:%.*]] = zext i8 [[ARG:%.*]] to i129
+; CHECK-NEXT:    [[SHL:%.*]] = shl nuw i129 1, [[EXT]]
 ; CHECK-NEXT:    ret i129 [[SHL]]
 ;
   %ext = zext i8 %arg to i129