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[PowerPC][GISel]fcmp support
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This patch also includes:
1: CRRegBank support
2: Some workarounds in PPC table gen for anyext/setcc patterns
   selection.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D140878
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@chenzheng1030
chenzheng1030 committed Jan 5, 2023
1 parent 5006d82 commit ac93a4e
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Showing 8 changed files with 292 additions and 19 deletions.
8 changes: 7 additions & 1 deletion llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp
View file
Expand Up @@ -99,7 +99,7 @@ static const TargetRegisterClass *getRegClass(LLT Ty, const RegisterBank *RB) {
if (RB->getID() == PPC::GPRRegBankID) {
if (Ty.getSizeInBits() == 64)
return &PPC::G8RCRegClass;
if (Ty.getSizeInBits() == 32)
if (Ty.getSizeInBits() <= 32)
return &PPC::GPRCRegClass;
}
if (RB->getID() == PPC::FPRRegBankID) {
Expand All @@ -108,6 +108,12 @@ static const TargetRegisterClass *getRegClass(LLT Ty, const RegisterBank *RB) {
if (Ty.getSizeInBits() == 64)
return &PPC::F8RCRegClass;
}
if (RB->getID() == PPC::CRRegBankID) {
if (Ty.getSizeInBits() == 1)
return &PPC::CRBITRCRegClass;
if (Ty.getSizeInBits() == 4)
return &PPC::CRRCRegClass;
}

llvm_unreachable("Unknown RegBank!");
}
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8 changes: 6 additions & 2 deletions llvm/lib/Target/PowerPC/GISel/PPCLegalizerInfo.cpp
View file
Expand Up @@ -20,6 +20,7 @@ using namespace LegalizeActions;
PPCLegalizerInfo::PPCLegalizerInfo(const PPCSubtarget &ST) {
using namespace TargetOpcode;
const LLT P0 = LLT::pointer(0, 64);
const LLT S1 = LLT::scalar(1);
const LLT S8 = LLT::scalar(8);
const LLT S16 = LLT::scalar(16);
const LLT S32 = LLT::scalar(32);
Expand All @@ -28,8 +29,8 @@ PPCLegalizerInfo::PPCLegalizerInfo(const PPCSubtarget &ST) {
getActionDefinitionsBuilder(G_CONSTANT)
.legalFor({S32, S64})
.clampScalar(0, S64, S64);
getActionDefinitionsBuilder({G_ZEXT, G_SEXT})
.legalForCartesianProduct({S64}, {S8, S16, S32})
getActionDefinitionsBuilder({G_ZEXT, G_SEXT, G_ANYEXT})
.legalForCartesianProduct({S64}, {S1, S8, S16, S32})
.clampScalar(0, S64, S64);
getActionDefinitionsBuilder({G_AND, G_OR, G_XOR})
.legalFor({S64})
Expand All @@ -41,6 +42,9 @@ PPCLegalizerInfo::PPCLegalizerInfo(const PPCSubtarget &ST) {
getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMUL, G_FDIV})
.legalFor({S32, S64});

getActionDefinitionsBuilder(G_FCMP).legalForCartesianProduct({S1},
{S32, S64});

getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI})
.legalForCartesianProduct({S64}, {S32, S64});

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13 changes: 13 additions & 0 deletions llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp
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Expand Up @@ -48,6 +48,9 @@ PPCRegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC,
case PPC::VSSRCRegClassID:
case PPC::F4RCRegClassID:
return getRegBank(PPC::FPRRegBankID);
case PPC::CRRCRegClassID:
case PPC::CRBITRCRegClassID:
return getRegBank(PPC::CRRegBankID);
default:
llvm_unreachable("Unexpected register class");
}
Expand Down Expand Up @@ -87,6 +90,7 @@ PPCRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
// Extension ops.
case TargetOpcode::G_SEXT:
case TargetOpcode::G_ZEXT:
case TargetOpcode::G_ANYEXT:
assert(NumOperands <= 3 &&
"This code is for instructions with 3 or less operands");
OperandsMapping = getValueMapping(PMI_GPR64);
Expand All @@ -102,6 +106,15 @@ PPCRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
OperandsMapping = getValueMapping(Size == 32 ? PMI_FPR32 : PMI_FPR64);
break;
}
case TargetOpcode::G_FCMP: {
unsigned CmpSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();

OperandsMapping = getOperandsMapping(
{getValueMapping(PMI_CR), nullptr,
getValueMapping(CmpSize == 32 ? PMI_FPR32 : PMI_FPR64),
getValueMapping(CmpSize == 32 ? PMI_FPR32 : PMI_FPR64)});
break;
}
case TargetOpcode::G_CONSTANT:
OperandsMapping = getOperandsMapping({getValueMapping(PMI_GPR64), nullptr});
break;
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1 change: 1 addition & 0 deletions llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.h
View file
Expand Up @@ -32,6 +32,7 @@ class PPCGenRegisterBankInfo : public RegisterBankInfo {
PMI_GPR64 = 2,
PMI_FPR32 = 3,
PMI_FPR64 = 4,
PMI_CR = 5,
PMI_Min = PMI_GPR32,
};

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2 changes: 2 additions & 0 deletions llvm/lib/Target/PowerPC/GISel/PPCRegisterBanks.td
View file
Expand Up @@ -15,3 +15,5 @@
def GPRRegBank : RegisterBank<"GPR", [G8RC, G8RC_NOX0]>;
/// Floating point Registers
def FPRRegBank : RegisterBank<"FPR", [VSSRC]>;
/// Condition Registers
def CRRegBank : RegisterBank<"CR", [CRRC]>;
4 changes: 4 additions & 0 deletions llvm/lib/Target/PowerPC/PPCGenRegisterBankInfo.def
View file
Expand Up @@ -22,6 +22,8 @@ RegisterBankInfo::PartialMapping PPCGenRegisterBankInfo::PartMappings[]{
{0, 32, PPC::FPRRegBank},
// 3: FPR 64-bit value
{0, 64, PPC::FPRRegBank},
// 4: CR 4-bit value
{0, 4, PPC::CRRegBank},
};

// ValueMappings.
Expand Down Expand Up @@ -55,6 +57,8 @@ RegisterBankInfo::ValueMapping PPCGenRegisterBankInfo::ValMappings[]{
{&PPCGenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
{&PPCGenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
{&PPCGenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
// 13: CR 4-bit value.
{&PPCGenRegisterBankInfo::PartMappings[PMI_CR - PMI_Min], 1},
};

// TODO Too simple!
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32 changes: 16 additions & 16 deletions llvm/lib/Target/PowerPC/PPCInstrInfo.td
View file
Expand Up @@ -3327,9 +3327,9 @@ def : Pat<(i64 (sext i1:$in)),
// FIXME: We should choose either a zext or a sext based on other constants
// already around.
def : Pat<(i32 (anyext i1:$in)),
(SELECT_I4 $in, (LI 1), (LI 0))>;
(SELECT_I4 i1:$in, (LI 1), (LI 0))>;
def : Pat<(i64 (anyext i1:$in)),
(SELECT_I8 $in, (LI8 1), (LI8 0))>;
(SELECT_I8 i1:$in, (LI8 1), (LI8 0))>;

// match setcc on i1 variables.
// CRANDC is:
Expand Down Expand Up @@ -3735,34 +3735,34 @@ defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETNE)),

multiclass FSetCCPat<SDPatternOperator SetCC, ValueType Ty, I FCmp> {
defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETUGE)),
(EXTRACT_SUBREG (FCmp $s1, $s2), sub_lt)>;
(EXTRACT_SUBREG (FCmp Ty:$s1, Ty:$s2), sub_lt)>;
defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETGE)),
(EXTRACT_SUBREG (FCmp $s1, $s2), sub_lt)>;
(EXTRACT_SUBREG (FCmp Ty:$s1, Ty:$s2), sub_lt)>;
defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETULE)),
(EXTRACT_SUBREG (FCmp $s1, $s2), sub_gt)>;
(EXTRACT_SUBREG (FCmp Ty:$s1, Ty:$s2), sub_gt)>;
defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETLE)),
(EXTRACT_SUBREG (FCmp $s1, $s2), sub_gt)>;
(EXTRACT_SUBREG (FCmp Ty:$s1, Ty:$s2), sub_gt)>;
defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETUNE)),
(EXTRACT_SUBREG (FCmp $s1, $s2), sub_eq)>;
(EXTRACT_SUBREG (FCmp Ty:$s1, Ty:$s2), sub_eq)>;
defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETNE)),
(EXTRACT_SUBREG (FCmp $s1, $s2), sub_eq)>;
(EXTRACT_SUBREG (FCmp Ty:$s1, Ty:$s2), sub_eq)>;
defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETO)),
(EXTRACT_SUBREG (FCmp $s1, $s2), sub_un)>;
(EXTRACT_SUBREG (FCmp Ty:$s1, Ty:$s2), sub_un)>;

def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETOLT)),
(EXTRACT_SUBREG (FCmp $s1, $s2), sub_lt)>;
(EXTRACT_SUBREG (FCmp Ty:$s1, Ty:$s2), sub_lt)>;
def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETLT)),
(EXTRACT_SUBREG (FCmp $s1, $s2), sub_lt)>;
(EXTRACT_SUBREG (FCmp Ty:$s1, Ty:$s2), sub_lt)>;
def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETOGT)),
(EXTRACT_SUBREG (FCmp $s1, $s2), sub_gt)>;
(EXTRACT_SUBREG (FCmp Ty:$s1, Ty:$s2), sub_gt)>;
def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETGT)),
(EXTRACT_SUBREG (FCmp $s1, $s2), sub_gt)>;
(EXTRACT_SUBREG (FCmp Ty:$s1, Ty:$s2), sub_gt)>;
def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETOEQ)),
(EXTRACT_SUBREG (FCmp $s1, $s2), sub_eq)>;
(EXTRACT_SUBREG (FCmp Ty:$s1, Ty:$s2), sub_eq)>;
def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETEQ)),
(EXTRACT_SUBREG (FCmp $s1, $s2), sub_eq)>;
(EXTRACT_SUBREG (FCmp Ty:$s1, Ty:$s2), sub_eq)>;
def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETUO)),
(EXTRACT_SUBREG (FCmp $s1, $s2), sub_un)>;
(EXTRACT_SUBREG (FCmp Ty:$s1, Ty:$s2), sub_un)>;
}

let Predicates = [HasFPU] in {
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