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AMDGPU: Bulk update some intrinsic tests to opaque pointers
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Done entirely with the script.
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@arsenm
arsenm committed Nov 28, 2022
1 parent b1a6f2a commit ad386a8
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Showing 158 changed files with 3,081 additions and 3,111 deletions.
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/AMDGPU/amd.endpgm.ll
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Expand Up @@ -40,7 +40,7 @@ define void @test1() {
unreachable
}

define amdgpu_kernel void @test2(i32* %p, i32 %x) {
define amdgpu_kernel void @test2(ptr %p, i32 %x) {
; GFX9-LABEL: test2:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dword s2, s[0:1], 0x2c
Expand Down Expand Up @@ -99,7 +99,7 @@ then:
unreachable

else:
store i32 %x, i32* %p
store i32 %x, ptr %p
ret void
}

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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/AMDGPU/cube.ll
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Expand Up @@ -12,7 +12,7 @@ declare float @llvm.amdgcn.cubema(float, float, float) #0
; GCN-DAG: v_cubetc_f32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
; GCN-DAG: v_cubema_f32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
; GCN: _store_dwordx4
define amdgpu_kernel void @cube(<4 x float> addrspace(1)* %out, float %a, float %b, float %c) #1 {
define amdgpu_kernel void @cube(ptr addrspace(1) %out, float %a, float %b, float %c) #1 {
%cubeid = call float @llvm.amdgcn.cubeid(float %a, float %b, float %c)
%cubesc = call float @llvm.amdgcn.cubesc(float %a, float %b, float %c)
%cubetc = call float @llvm.amdgcn.cubetc(float %a, float %b, float %c)
Expand All @@ -22,7 +22,7 @@ define amdgpu_kernel void @cube(<4 x float> addrspace(1)* %out, float %a, float
%vec1 = insertelement <4 x float> %vec0, float %cubesc, i32 1
%vec2 = insertelement <4 x float> %vec1, float %cubetc, i32 2
%vec3 = insertelement <4 x float> %vec2, float %cubema, i32 3
store <4 x float> %vec3, <4 x float> addrspace(1)* %out
store <4 x float> %vec3, ptr addrspace(1) %out
ret void
}

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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/AMDGPU/llvm.amdgcn.alignbyte.ll
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Expand Up @@ -4,9 +4,9 @@ declare i32 @llvm.amdgcn.alignbyte(i32, i32, i32) #0

; GCN-LABEL: {{^}}v_alignbyte_b32:
; GCN: v_alignbyte_b32 {{[vs][0-9]+}}, {{[vs][0-9]+}}, {{[vs][0-9]+}}
define amdgpu_kernel void @v_alignbyte_b32(i32 addrspace(1)* %out, i32 %src1, i32 %src2, i32 %src3) #1 {
define amdgpu_kernel void @v_alignbyte_b32(ptr addrspace(1) %out, i32 %src1, i32 %src2, i32 %src3) #1 {
%val = call i32 @llvm.amdgcn.alignbyte(i32 %src1, i32 %src2, i32 %src3) #0
store i32 %val, i32 addrspace(1)* %out
store i32 %val, ptr addrspace(1) %out
ret void
}

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12 changes: 6 additions & 6 deletions llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.csub.ll
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Expand Up @@ -2,7 +2,7 @@
; RUN: llc < %s -march=amdgcn -mcpu=gfx1031 -verify-machineinstrs | FileCheck %s -check-prefix=GCN

declare i32 @llvm.amdgcn.buffer.atomic.csub(i32, <4 x i32>, i32, i32, i1)
declare i32 @llvm.amdgcn.global.atomic.csub(i32 addrspace(1)*, i32)
declare i32 @llvm.amdgcn.global.atomic.csub(ptr addrspace(1), i32)

; GCN-LABEL: {{^}}buffer_atomic_csub:
; GCN: buffer_atomic_csub v0, v1, s[0:3], 0 idxen glc
Expand All @@ -22,17 +22,17 @@ main_body:

; GCN-LABEL: {{^}}global_atomic_csub:
; GCN: global_atomic_csub v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9:]+}}, s{{\[[0-9]+:[0-9]+\]}} glc
define amdgpu_kernel void @global_atomic_csub(i32 addrspace(1)* %ptr, i32 %data) {
define amdgpu_kernel void @global_atomic_csub(ptr addrspace(1) %ptr, i32 %data) {
main_body:
%ret = call i32 @llvm.amdgcn.global.atomic.csub(i32 addrspace(1)* %ptr, i32 %data)
%ret = call i32 @llvm.amdgcn.global.atomic.csub(ptr addrspace(1) %ptr, i32 %data)
ret void
}

; GCN-LABEL: {{^}}global_atomic_csub_off4:
; GCN: global_atomic_csub v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}} offset:4 glc
define amdgpu_kernel void @global_atomic_csub_off4(i32 addrspace(1)* %ptr, i32 %data) {
define amdgpu_kernel void @global_atomic_csub_off4(ptr addrspace(1) %ptr, i32 %data) {
main_body:
%p = getelementptr i32, i32 addrspace(1)* %ptr, i64 1
%ret = call i32 @llvm.amdgcn.global.atomic.csub(i32 addrspace(1)* %p, i32 %data)
%p = getelementptr i32, ptr addrspace(1) %ptr, i64 1
%ret = call i32 @llvm.amdgcn.global.atomic.csub(ptr addrspace(1) %p, i32 %data)
ret void
}
256 changes: 128 additions & 128 deletions llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.dec.ll
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36 changes: 18 additions & 18 deletions llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.fadd.gfx90a.ll
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Expand Up @@ -3,8 +3,8 @@

declare float @llvm.amdgcn.buffer.atomic.fadd.f32(float, <4 x i32>, i32, i32, i1)
declare <2 x half> @llvm.amdgcn.buffer.atomic.fadd.v2f16(<2 x half>, <4 x i32>, i32, i32, i1)
declare float @llvm.amdgcn.global.atomic.fadd.f32.p1f32.f32(float addrspace(1)*, float)
declare <2 x half> @llvm.amdgcn.global.atomic.fadd.v2f16.p1v2f16.v2f16(<2 x half> addrspace(1)*, <2 x half>)
declare float @llvm.amdgcn.global.atomic.fadd.f32.p1.f32(ptr addrspace(1), float)
declare <2 x half> @llvm.amdgcn.global.atomic.fadd.v2f16.p1.v2f16(ptr addrspace(1), <2 x half>)

; GFX908: LLVM ERROR: Cannot select: {{.+}}: f32,ch = BUFFER_ATOMIC_FADD

Expand Down Expand Up @@ -42,52 +42,52 @@ main_body:

; GFX90A-LABEL: {{^}}global_atomic_add_f32:
; GFX90A: global_atomic_add_f32 v0, v[0:1], v2, off glc
define amdgpu_ps float @global_atomic_add_f32(float addrspace(1)* %ptr, float %data) {
define amdgpu_ps float @global_atomic_add_f32(ptr addrspace(1) %ptr, float %data) {
main_body:
%ret = call float @llvm.amdgcn.global.atomic.fadd.f32.p1f32.f32(float addrspace(1)* %ptr, float %data)
%ret = call float @llvm.amdgcn.global.atomic.fadd.f32.p1.f32(ptr addrspace(1) %ptr, float %data)
ret float %ret
}

; GFX90A-LABEL: {{^}}global_atomic_add_f32_off4:
; GFX90A: global_atomic_add_f32 v0, v[0:1], v2, off offset:4 glc
define amdgpu_ps float @global_atomic_add_f32_off4(float addrspace(1)* %ptr, float %data) {
define amdgpu_ps float @global_atomic_add_f32_off4(ptr addrspace(1) %ptr, float %data) {
main_body:
%p = getelementptr float, float addrspace(1)* %ptr, i64 1
%ret = call float @llvm.amdgcn.global.atomic.fadd.f32.p1f32.f32(float addrspace(1)* %p, float %data)
%p = getelementptr float, ptr addrspace(1) %ptr, i64 1
%ret = call float @llvm.amdgcn.global.atomic.fadd.f32.p1.f32(ptr addrspace(1) %p, float %data)
ret float %ret
}

; GFX90A-LABEL: {{^}}global_atomic_add_f32_offneg4:
; GFX90A: global_atomic_add_f32 v0, v[0:1], v2, off offset:-4 glc
define amdgpu_ps float @global_atomic_add_f32_offneg4(float addrspace(1)* %ptr, float %data) {
define amdgpu_ps float @global_atomic_add_f32_offneg4(ptr addrspace(1) %ptr, float %data) {
main_body:
%p = getelementptr float, float addrspace(1)* %ptr, i64 -1
%ret = call float @llvm.amdgcn.global.atomic.fadd.f32.p1f32.f32(float addrspace(1)* %p, float %data)
%p = getelementptr float, ptr addrspace(1) %ptr, i64 -1
%ret = call float @llvm.amdgcn.global.atomic.fadd.f32.p1.f32(ptr addrspace(1) %p, float %data)
ret float %ret
}

; GFX90A-LABEL: {{^}}global_atomic_pk_add_v2f16:
; GFX90A: global_atomic_pk_add_f16 v0, v[0:1], v2, off glc
define amdgpu_ps <2 x half> @global_atomic_pk_add_v2f16(<2 x half> addrspace(1)* %ptr, <2 x half> %data) {
define amdgpu_ps <2 x half> @global_atomic_pk_add_v2f16(ptr addrspace(1) %ptr, <2 x half> %data) {
main_body:
%ret = call <2 x half> @llvm.amdgcn.global.atomic.fadd.v2f16.p1v2f16.v2f16(<2 x half> addrspace(1)* %ptr, <2 x half> %data)
%ret = call <2 x half> @llvm.amdgcn.global.atomic.fadd.v2f16.p1.v2f16(ptr addrspace(1) %ptr, <2 x half> %data)
ret <2 x half> %ret
}

; GFX90A-LABEL: {{^}}global_atomic_pk_add_v2f16_off4:
; GFX90A: global_atomic_pk_add_f16 v0, v[0:1], v2, off offset:4 glc
define amdgpu_ps <2 x half> @global_atomic_pk_add_v2f16_off4(<2 x half> addrspace(1)* %ptr, <2 x half> %data) {
define amdgpu_ps <2 x half> @global_atomic_pk_add_v2f16_off4(ptr addrspace(1) %ptr, <2 x half> %data) {
main_body:
%p = getelementptr <2 x half>, <2 x half> addrspace(1)* %ptr, i64 1
%ret = call <2 x half> @llvm.amdgcn.global.atomic.fadd.v2f16.p1v2f16.v2f16(<2 x half> addrspace(1)* %p, <2 x half> %data)
%p = getelementptr <2 x half>, ptr addrspace(1) %ptr, i64 1
%ret = call <2 x half> @llvm.amdgcn.global.atomic.fadd.v2f16.p1.v2f16(ptr addrspace(1) %p, <2 x half> %data)
ret <2 x half> %ret
}

; GFX90A-LABEL: {{^}}global_atomic_pk_add_v2f16_offneg4:
; GFX90A: global_atomic_pk_add_f16 v0, v[0:1], v2, off offset:-4 glc
define amdgpu_ps <2 x half> @global_atomic_pk_add_v2f16_offneg4(<2 x half> addrspace(1)* %ptr, <2 x half> %data) {
define amdgpu_ps <2 x half> @global_atomic_pk_add_v2f16_offneg4(ptr addrspace(1) %ptr, <2 x half> %data) {
main_body:
%p = getelementptr <2 x half>, <2 x half> addrspace(1)* %ptr, i64 -1
%ret = call <2 x half> @llvm.amdgcn.global.atomic.fadd.v2f16.p1v2f16.v2f16(<2 x half> addrspace(1)* %p, <2 x half> %data)
%p = getelementptr <2 x half>, ptr addrspace(1) %ptr, i64 -1
%ret = call <2 x half> @llvm.amdgcn.global.atomic.fadd.v2f16.p1.v2f16(ptr addrspace(1) %p, <2 x half> %data)
ret <2 x half> %ret
}
46 changes: 23 additions & 23 deletions llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.fadd.ll
View file
Expand Up @@ -3,9 +3,9 @@

declare float @llvm.amdgcn.buffer.atomic.fadd.f32(float, <4 x i32>, i32, i32, i1)
declare <2 x half> @llvm.amdgcn.buffer.atomic.fadd.v2f16(<2 x half>, <4 x i32>, i32, i32, i1)
declare float @llvm.amdgcn.global.atomic.fadd.f32.p1f32.f32(float addrspace(1)*, float)
declare <2 x half> @llvm.amdgcn.global.atomic.fadd.v2f16.p1v2f16.v2f16(<2 x half> addrspace(1)*, <2 x half>)
declare float @llvm.amdgcn.flat.atomic.fadd.f32.p0f32.f32(float*, float)
declare float @llvm.amdgcn.global.atomic.fadd.f32.p1.f32(ptr addrspace(1), float)
declare <2 x half> @llvm.amdgcn.global.atomic.fadd.v2f16.p1.v2f16(ptr addrspace(1), <2 x half>)
declare float @llvm.amdgcn.flat.atomic.fadd.f32.p0.f32(ptr, float)

; GCN-LABEL: {{^}}buffer_atomic_add_f32:
; GCN: buffer_atomic_add_f32 v0, v1, s[0:3], 0 idxen
Expand Down Expand Up @@ -41,69 +41,69 @@ main_body:

; GCN-LABEL: {{^}}global_atomic_add_f32:
; GCN: global_atomic_add_f32 v{{[0-9]+}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}
define amdgpu_kernel void @global_atomic_add_f32(float addrspace(1)* %ptr, float %data) {
define amdgpu_kernel void @global_atomic_add_f32(ptr addrspace(1) %ptr, float %data) {
main_body:
%ret = call float @llvm.amdgcn.global.atomic.fadd.f32.p1f32.f32(float addrspace(1)* %ptr, float %data)
%ret = call float @llvm.amdgcn.global.atomic.fadd.f32.p1.f32(ptr addrspace(1) %ptr, float %data)
ret void
}

; GCN-LABEL: {{^}}global_atomic_add_f32_off4:
; GCN: global_atomic_add_f32 v{{[0-9]+}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}} offset:4
define amdgpu_kernel void @global_atomic_add_f32_off4(float addrspace(1)* %ptr, float %data) {
define amdgpu_kernel void @global_atomic_add_f32_off4(ptr addrspace(1) %ptr, float %data) {
main_body:
%p = getelementptr float, float addrspace(1)* %ptr, i64 1
%ret = call float @llvm.amdgcn.global.atomic.fadd.f32.p1f32.f32(float addrspace(1)* %p, float %data)
%p = getelementptr float, ptr addrspace(1) %ptr, i64 1
%ret = call float @llvm.amdgcn.global.atomic.fadd.f32.p1.f32(ptr addrspace(1) %p, float %data)
ret void
}

; GCN-LABEL: {{^}}global_atomic_add_f32_offneg4:
; GCN: global_atomic_add_f32 v{{[0-9]+}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}} offset:-4
define amdgpu_kernel void @global_atomic_add_f32_offneg4(float addrspace(1)* %ptr, float %data) {
define amdgpu_kernel void @global_atomic_add_f32_offneg4(ptr addrspace(1) %ptr, float %data) {
main_body:
%p = getelementptr float, float addrspace(1)* %ptr, i64 -1
%ret = call float @llvm.amdgcn.global.atomic.fadd.f32.p1f32.f32(float addrspace(1)* %p, float %data)
%p = getelementptr float, ptr addrspace(1) %ptr, i64 -1
%ret = call float @llvm.amdgcn.global.atomic.fadd.f32.p1.f32(ptr addrspace(1) %p, float %data)
ret void
}

; GCN-LABEL: {{^}}global_atomic_pk_add_v2f16:
; GCN: global_atomic_pk_add_f16 v{{[0-9]+}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @global_atomic_pk_add_v2f16(<2 x half> addrspace(1)* %ptr, <2 x half> %data) {
define amdgpu_kernel void @global_atomic_pk_add_v2f16(ptr addrspace(1) %ptr, <2 x half> %data) {
main_body:
%ret = call <2 x half> @llvm.amdgcn.global.atomic.fadd.v2f16.p1v2f16.v2f16(<2 x half> addrspace(1)* %ptr, <2 x half> %data)
%ret = call <2 x half> @llvm.amdgcn.global.atomic.fadd.v2f16.p1.v2f16(ptr addrspace(1) %ptr, <2 x half> %data)
ret void
}

; GCN-LABEL: {{^}}global_atomic_pk_add_v2f16_off4:
; GCN: global_atomic_pk_add_f16 v{{[0-9]+}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}} offset:4
define amdgpu_kernel void @global_atomic_pk_add_v2f16_off4(<2 x half> addrspace(1)* %ptr, <2 x half> %data) {
define amdgpu_kernel void @global_atomic_pk_add_v2f16_off4(ptr addrspace(1) %ptr, <2 x half> %data) {
main_body:
%p = getelementptr <2 x half>, <2 x half> addrspace(1)* %ptr, i64 1
%ret = call <2 x half> @llvm.amdgcn.global.atomic.fadd.v2f16.p1v2f16.v2f16(<2 x half> addrspace(1)* %p, <2 x half> %data)
%p = getelementptr <2 x half>, ptr addrspace(1) %ptr, i64 1
%ret = call <2 x half> @llvm.amdgcn.global.atomic.fadd.v2f16.p1.v2f16(ptr addrspace(1) %p, <2 x half> %data)
ret void
}

; GCN-LABEL: {{^}}global_atomic_pk_add_v2f16_offneg4:
; GCN: global_atomic_pk_add_f16 v{{[0-9]+}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}} offset:-4{{$}}
define amdgpu_kernel void @global_atomic_pk_add_v2f16_offneg4(<2 x half> addrspace(1)* %ptr, <2 x half> %data) {
define amdgpu_kernel void @global_atomic_pk_add_v2f16_offneg4(ptr addrspace(1) %ptr, <2 x half> %data) {
main_body:
%p = getelementptr <2 x half>, <2 x half> addrspace(1)* %ptr, i64 -1
%ret = call <2 x half> @llvm.amdgcn.global.atomic.fadd.v2f16.p1v2f16.v2f16(<2 x half> addrspace(1)* %p, <2 x half> %data)
%p = getelementptr <2 x half>, ptr addrspace(1) %ptr, i64 -1
%ret = call <2 x half> @llvm.amdgcn.global.atomic.fadd.v2f16.p1.v2f16(ptr addrspace(1) %p, <2 x half> %data)
ret void
}

; Make sure this artificially selects with an incorrect subtarget, but
; the feature set.
; GCN-LABEL: {{^}}global_atomic_fadd_f32_wrong_subtarget:
; GCN: global_atomic_add_f32 v{{[0-9]+}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @global_atomic_fadd_f32_wrong_subtarget(float addrspace(1)* %ptr, float %data) #0 {
%ret = call float @llvm.amdgcn.global.atomic.fadd.f32.p1f32.f32(float addrspace(1)* %ptr, float %data)
define amdgpu_kernel void @global_atomic_fadd_f32_wrong_subtarget(ptr addrspace(1) %ptr, float %data) #0 {
%ret = call float @llvm.amdgcn.global.atomic.fadd.f32.p1.f32(ptr addrspace(1) %ptr, float %data)
ret void
}

; GCN-LABEL: {{^}}flat_atomic_fadd_f32_wrong_subtarget:
; GCN: flat_atomic_add_f32 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}
define amdgpu_kernel void @flat_atomic_fadd_f32_wrong_subtarget(float* %ptr, float %data) #1 {
%ret = call float @llvm.amdgcn.flat.atomic.fadd.f32.p0f32.f32(float* %ptr, float %data)
define amdgpu_kernel void @flat_atomic_fadd_f32_wrong_subtarget(ptr %ptr, float %data) #1 {
%ret = call float @llvm.amdgcn.flat.atomic.fadd.f32.p0.f32(ptr %ptr, float %data)
ret void
}

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