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Summary: Without this patch, LoopVectorizer in certain cases (see loop-vectorize.ll) produces code with complex control flow which hurts later optimizations. Since NVPTX doesn't have vector registers in LLVM's sense (NVPTXTTI::getRegisterBitWidth(true) == 32), we for now declare no vector registers to effectively disable loop vectorization. Reviewers: jholewinski Subscribers: jingyue, llvm-commits, jholewinski Differential Revision: http://reviews.llvm.org/D11089 llvm-svn: 241884
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Jingyue Wu
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Jul 10, 2015
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; RUN: opt < %s -O3 -S | FileCheck %s | ||
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target datalayout = "e-i64:64-v16:16-v32:32-n16:32:64" | ||
target triple = "nvptx64-nvidia-cuda" | ||
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define void @no_vectorization(i32 %n, i32 %a, i32 %b) { | ||
; CHECK-LABEL: no_vectorization( | ||
; CHECK-NOT: <4 x i32> | ||
; CHECK-NOT: <4 x i1> | ||
entry: | ||
%cmp.5 = icmp sgt i32 %n, 0 | ||
br i1 %cmp.5, label %for.body.preheader, label %for.cond.cleanup | ||
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for.body.preheader: ; preds = %entry | ||
br label %for.body | ||
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for.cond.cleanup.loopexit: ; preds = %for.body | ||
br label %for.cond.cleanup | ||
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for.cond.cleanup: ; preds = %for.cond.cleanup.loopexit, %entry | ||
ret void | ||
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for.body: ; preds = %for.body.preheader, %for.body | ||
%i.06 = phi i32 [ %inc, %for.body ], [ 0, %for.body.preheader ] | ||
%add = add nsw i32 %i.06, %a | ||
%mul = mul nsw i32 %add, %b | ||
%cmp1 = icmp sgt i32 %mul, -1 | ||
tail call void @llvm.assume(i1 %cmp1) | ||
%inc = add nuw nsw i32 %i.06, 1 | ||
%exitcond = icmp eq i32 %inc, %n | ||
br i1 %exitcond, label %for.cond.cleanup.loopexit, label %for.body | ||
} | ||
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declare void @llvm.assume(i1) #0 | ||
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attributes #0 = { nounwind } | ||
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!nvvm.annotations = !{!0} | ||
!0 = !{void (i32, i32, i32)* @no_vectorization, !"kernel", i32 1} |