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[X86] Add test coverage for rotl/rotr with freeze
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@RKSimon
RKSimon committed Oct 22, 2022
1 parent 2732fb7 commit ae946ae
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124 changes: 124 additions & 0 deletions llvm/test/CodeGen/X86/freeze-binary.ll
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Expand Up @@ -625,3 +625,127 @@ define <4 x i32> @freeze_lshr_vec_outofrange(<4 x i32> %a0) nounwind {
%z = lshr <4 x i32> %y, <i32 2, i32 2, i32 2, i32 2>
ret <4 x i32> %z
}

define i32 @freeze_rotl(i32 %a0) nounwind {
; X86-LABEL: freeze_rotl:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: roll $5, %eax
; X86-NEXT: roll $5, %eax
; X86-NEXT: retl
;
; X64-LABEL: freeze_rotl:
; X64: # %bb.0:
; X64-NEXT: movl %edi, %eax
; X64-NEXT: roll $5, %eax
; X64-NEXT: roll $5, %eax
; X64-NEXT: retq
%x = call i32 @llvm.fshl.i32(i32 %a0, i32 %a0, i32 5)
%y = freeze i32 %x
%z = call i32 @llvm.fshl.i32(i32 %y, i32 %y, i32 5)
ret i32 %z
}
declare i32 @llvm.fshl.i32(i32, i32, i32)

define <4 x i32> @freeze_rotl_vec(<4 x i32> %a0) nounwind {
; X86-LABEL: freeze_rotl_vec:
; X86: # %bb.0:
; X86-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
; X86-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,3,2,3]
; X86-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-NEXT: pshufd {{.*#+}} xmm3 = xmm1[1,3,2,3]
; X86-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
; X86-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; X86-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; X86-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; X86-NEXT: por %xmm2, %xmm0
; X86-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
; X86-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,3,2,3]
; X86-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-NEXT: pshufd {{.*#+}} xmm3 = xmm1[1,3,2,3]
; X86-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
; X86-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; X86-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; X86-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; X86-NEXT: por %xmm2, %xmm0
; X86-NEXT: retl
;
; X64-LABEL: freeze_rotl_vec:
; X64: # %bb.0:
; X64-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; X64-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-NEXT: vpor %xmm1, %xmm0, %xmm0
; X64-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; X64-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-NEXT: vpor %xmm1, %xmm0, %xmm0
; X64-NEXT: retq
%x = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %a0, <4 x i32> %a0, <4 x i32> <i32 0, i32 1, i32 2, i32 3>)
%y = freeze <4 x i32> %x
%z = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %y, <4 x i32> %y, <4 x i32> <i32 30, i32 29, i32 28, i32 27>)
ret <4 x i32> %z
}
declare <4 x i32> @llvm.fshl.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)

define i32 @freeze_rotr(i32 %a0) nounwind {
; X86-LABEL: freeze_rotr:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: rorl $11, %eax
; X86-NEXT: rorl $13, %eax
; X86-NEXT: retl
;
; X64-LABEL: freeze_rotr:
; X64: # %bb.0:
; X64-NEXT: movl %edi, %eax
; X64-NEXT: rorl $11, %eax
; X64-NEXT: rorl $13, %eax
; X64-NEXT: retq
%x = call i32 @llvm.fshr.i32(i32 %a0, i32 %a0, i32 11)
%y = freeze i32 %x
%z = call i32 @llvm.fshr.i32(i32 %y, i32 %y, i32 13)
ret i32 %z
}
declare i32 @llvm.fshr.i32(i32, i32, i32)

define <4 x i32> @freeze_rotr_vec(<4 x i32> %a0) nounwind {
; X86-LABEL: freeze_rotr_vec:
; X86: # %bb.0:
; X86-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
; X86-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,3,2,3]
; X86-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-NEXT: pshufd {{.*#+}} xmm3 = xmm1[1,3,2,3]
; X86-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
; X86-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; X86-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; X86-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; X86-NEXT: por %xmm2, %xmm0
; X86-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
; X86-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,3,2,3]
; X86-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-NEXT: pshufd {{.*#+}} xmm3 = xmm1[1,3,2,3]
; X86-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
; X86-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; X86-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; X86-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; X86-NEXT: por %xmm2, %xmm0
; X86-NEXT: retl
;
; X64-LABEL: freeze_rotr_vec:
; X64: # %bb.0:
; X64-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; X64-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-NEXT: vpor %xmm1, %xmm0, %xmm0
; X64-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; X64-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-NEXT: vpor %xmm1, %xmm0, %xmm0
; X64-NEXT: retq
%x = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %a0, <4 x i32> %a0, <4 x i32> <i32 0, i32 1, i32 2, i32 3>)
%y = freeze <4 x i32> %x
%z = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %y, <4 x i32> %y, <4 x i32> <i32 31, i32 30, i32 29, i32 28>)
ret <4 x i32> %z
}
declare <4 x i32> @llvm.fshr.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)

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