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[RISCV] Generate pseudo instruction li
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Add an alias of `addi [x], zero, imm` to generate pseudo
instruction li, which makes assembly mush more readable.
For existed tests, users can update them by running script
`llvm/utils/update_llc_test_checks.py`.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D112692
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@pcwang-thead
pcwang-thead committed Nov 22, 2021
1 parent 49e3838 commit af0ecfc
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Showing 222 changed files with 5,756 additions and 5,716 deletions.
1 change: 1 addition & 0 deletions llvm/lib/Target/RISCV/RISCVInstrInfo.td
View file
Expand Up @@ -705,6 +705,7 @@ def PseudoLD : PseudoLoad<"ld">;
def PseudoSD : PseudoStore<"sd">;
} // Predicates = [IsRV64]

def : InstAlias<"li $rd, $imm", (ADDI GPR:$rd, X0, simm12:$imm)>;
def : InstAlias<"mv $rd, $rs", (ADDI GPR:$rd, GPR:$rs, 0)>;
def : InstAlias<"not $rd, $rs", (XORI GPR:$rd, GPR:$rs, -1)>;
def : InstAlias<"neg $rd, $rs", (SUB GPR:$rd, X0, GPR:$rs)>;
Expand Down
70 changes: 35 additions & 35 deletions llvm/test/CodeGen/RISCV/addimm-mulimm.ll
View file
Expand Up @@ -10,14 +10,14 @@
define i32 @add_mul_combine_accept_a1(i32 %x) {
; RV32IMB-LABEL: add_mul_combine_accept_a1:
; RV32IMB: # %bb.0:
; RV32IMB-NEXT: addi a1, zero, 29
; RV32IMB-NEXT: li a1, 29
; RV32IMB-NEXT: mul a0, a0, a1
; RV32IMB-NEXT: addi a0, a0, 1073
; RV32IMB-NEXT: ret
;
; RV64IMB-LABEL: add_mul_combine_accept_a1:
; RV64IMB: # %bb.0:
; RV64IMB-NEXT: addi a1, zero, 29
; RV64IMB-NEXT: li a1, 29
; RV64IMB-NEXT: mulw a0, a0, a1
; RV64IMB-NEXT: addiw a0, a0, 1073
; RV64IMB-NEXT: ret
Expand All @@ -29,14 +29,14 @@ define i32 @add_mul_combine_accept_a1(i32 %x) {
define signext i32 @add_mul_combine_accept_a2(i32 signext %x) {
; RV32IMB-LABEL: add_mul_combine_accept_a2:
; RV32IMB: # %bb.0:
; RV32IMB-NEXT: addi a1, zero, 29
; RV32IMB-NEXT: li a1, 29
; RV32IMB-NEXT: mul a0, a0, a1
; RV32IMB-NEXT: addi a0, a0, 1073
; RV32IMB-NEXT: ret
;
; RV64IMB-LABEL: add_mul_combine_accept_a2:
; RV64IMB: # %bb.0:
; RV64IMB-NEXT: addi a1, zero, 29
; RV64IMB-NEXT: li a1, 29
; RV64IMB-NEXT: mulw a0, a0, a1
; RV64IMB-NEXT: addiw a0, a0, 1073
; RV64IMB-NEXT: ret
Expand All @@ -48,7 +48,7 @@ define signext i32 @add_mul_combine_accept_a2(i32 signext %x) {
define i64 @add_mul_combine_accept_a3(i64 %x) {
; RV32IMB-LABEL: add_mul_combine_accept_a3:
; RV32IMB: # %bb.0:
; RV32IMB-NEXT: addi a2, zero, 29
; RV32IMB-NEXT: li a2, 29
; RV32IMB-NEXT: mul a1, a1, a2
; RV32IMB-NEXT: mulhu a3, a0, a2
; RV32IMB-NEXT: add a1, a3, a1
Expand All @@ -60,7 +60,7 @@ define i64 @add_mul_combine_accept_a3(i64 %x) {
;
; RV64IMB-LABEL: add_mul_combine_accept_a3:
; RV64IMB: # %bb.0:
; RV64IMB-NEXT: addi a1, zero, 29
; RV64IMB-NEXT: li a1, 29
; RV64IMB-NEXT: mul a0, a0, a1
; RV64IMB-NEXT: addi a0, a0, 1073
; RV64IMB-NEXT: ret
Expand All @@ -72,7 +72,7 @@ define i64 @add_mul_combine_accept_a3(i64 %x) {
define i32 @add_mul_combine_accept_b1(i32 %x) {
; RV32IMB-LABEL: add_mul_combine_accept_b1:
; RV32IMB: # %bb.0:
; RV32IMB-NEXT: addi a1, zero, 23
; RV32IMB-NEXT: li a1, 23
; RV32IMB-NEXT: mul a0, a0, a1
; RV32IMB-NEXT: lui a1, 50
; RV32IMB-NEXT: addi a1, a1, 1119
Expand All @@ -81,7 +81,7 @@ define i32 @add_mul_combine_accept_b1(i32 %x) {
;
; RV64IMB-LABEL: add_mul_combine_accept_b1:
; RV64IMB: # %bb.0:
; RV64IMB-NEXT: addi a1, zero, 23
; RV64IMB-NEXT: li a1, 23
; RV64IMB-NEXT: mulw a0, a0, a1
; RV64IMB-NEXT: lui a1, 50
; RV64IMB-NEXT: addiw a1, a1, 1119
Expand All @@ -95,7 +95,7 @@ define i32 @add_mul_combine_accept_b1(i32 %x) {
define signext i32 @add_mul_combine_accept_b2(i32 signext %x) {
; RV32IMB-LABEL: add_mul_combine_accept_b2:
; RV32IMB: # %bb.0:
; RV32IMB-NEXT: addi a1, zero, 23
; RV32IMB-NEXT: li a1, 23
; RV32IMB-NEXT: mul a0, a0, a1
; RV32IMB-NEXT: lui a1, 50
; RV32IMB-NEXT: addi a1, a1, 1119
Expand All @@ -104,7 +104,7 @@ define signext i32 @add_mul_combine_accept_b2(i32 signext %x) {
;
; RV64IMB-LABEL: add_mul_combine_accept_b2:
; RV64IMB: # %bb.0:
; RV64IMB-NEXT: addi a1, zero, 23
; RV64IMB-NEXT: li a1, 23
; RV64IMB-NEXT: mulw a0, a0, a1
; RV64IMB-NEXT: lui a1, 50
; RV64IMB-NEXT: addiw a1, a1, 1119
Expand All @@ -118,7 +118,7 @@ define signext i32 @add_mul_combine_accept_b2(i32 signext %x) {
define i64 @add_mul_combine_accept_b3(i64 %x) {
; RV32IMB-LABEL: add_mul_combine_accept_b3:
; RV32IMB: # %bb.0:
; RV32IMB-NEXT: addi a2, zero, 23
; RV32IMB-NEXT: li a2, 23
; RV32IMB-NEXT: mul a1, a1, a2
; RV32IMB-NEXT: mulhu a3, a0, a2
; RV32IMB-NEXT: add a1, a3, a1
Expand All @@ -132,7 +132,7 @@ define i64 @add_mul_combine_accept_b3(i64 %x) {
;
; RV64IMB-LABEL: add_mul_combine_accept_b3:
; RV64IMB: # %bb.0:
; RV64IMB-NEXT: addi a1, zero, 23
; RV64IMB-NEXT: li a1, 23
; RV64IMB-NEXT: mul a0, a0, a1
; RV64IMB-NEXT: lui a1, 50
; RV64IMB-NEXT: addiw a1, a1, 1119
Expand All @@ -147,14 +147,14 @@ define i32 @add_mul_combine_reject_a1(i32 %x) {
; RV32IMB-LABEL: add_mul_combine_reject_a1:
; RV32IMB: # %bb.0:
; RV32IMB-NEXT: addi a0, a0, 1971
; RV32IMB-NEXT: addi a1, zero, 29
; RV32IMB-NEXT: li a1, 29
; RV32IMB-NEXT: mul a0, a0, a1
; RV32IMB-NEXT: ret
;
; RV64IMB-LABEL: add_mul_combine_reject_a1:
; RV64IMB: # %bb.0:
; RV64IMB-NEXT: addiw a0, a0, 1971
; RV64IMB-NEXT: addi a1, zero, 29
; RV64IMB-NEXT: li a1, 29
; RV64IMB-NEXT: mulw a0, a0, a1
; RV64IMB-NEXT: ret
%tmp0 = add i32 %x, 1971
Expand All @@ -166,14 +166,14 @@ define signext i32 @add_mul_combine_reject_a2(i32 signext %x) {
; RV32IMB-LABEL: add_mul_combine_reject_a2:
; RV32IMB: # %bb.0:
; RV32IMB-NEXT: addi a0, a0, 1971
; RV32IMB-NEXT: addi a1, zero, 29
; RV32IMB-NEXT: li a1, 29
; RV32IMB-NEXT: mul a0, a0, a1
; RV32IMB-NEXT: ret
;
; RV64IMB-LABEL: add_mul_combine_reject_a2:
; RV64IMB: # %bb.0:
; RV64IMB-NEXT: addiw a0, a0, 1971
; RV64IMB-NEXT: addi a1, zero, 29
; RV64IMB-NEXT: li a1, 29
; RV64IMB-NEXT: mulw a0, a0, a1
; RV64IMB-NEXT: ret
%tmp0 = add i32 %x, 1971
Expand All @@ -184,7 +184,7 @@ define signext i32 @add_mul_combine_reject_a2(i32 signext %x) {
define i64 @add_mul_combine_reject_a3(i64 %x) {
; RV32IMB-LABEL: add_mul_combine_reject_a3:
; RV32IMB: # %bb.0:
; RV32IMB-NEXT: addi a2, zero, 29
; RV32IMB-NEXT: li a2, 29
; RV32IMB-NEXT: mul a1, a1, a2
; RV32IMB-NEXT: mulhu a3, a0, a2
; RV32IMB-NEXT: add a1, a3, a1
Expand All @@ -199,7 +199,7 @@ define i64 @add_mul_combine_reject_a3(i64 %x) {
; RV64IMB-LABEL: add_mul_combine_reject_a3:
; RV64IMB: # %bb.0:
; RV64IMB-NEXT: addi a0, a0, 1971
; RV64IMB-NEXT: addi a1, zero, 29
; RV64IMB-NEXT: li a1, 29
; RV64IMB-NEXT: mul a0, a0, a1
; RV64IMB-NEXT: ret
%tmp0 = add i64 %x, 1971
Expand Down Expand Up @@ -250,7 +250,7 @@ define signext i32 @add_mul_combine_reject_c2(i32 signext %x) {
define i64 @add_mul_combine_reject_c3(i64 %x) {
; RV32IMB-LABEL: add_mul_combine_reject_c3:
; RV32IMB: # %bb.0:
; RV32IMB-NEXT: addi a2, zero, 73
; RV32IMB-NEXT: li a2, 73
; RV32IMB-NEXT: mul a1, a1, a2
; RV32IMB-NEXT: mulhu a3, a0, a2
; RV32IMB-NEXT: add a1, a3, a1
Expand Down Expand Up @@ -314,7 +314,7 @@ define signext i32 @add_mul_combine_reject_d2(i32 signext %x) {
define i64 @add_mul_combine_reject_d3(i64 %x) {
; RV32IMB-LABEL: add_mul_combine_reject_d3:
; RV32IMB: # %bb.0:
; RV32IMB-NEXT: addi a2, zero, 192
; RV32IMB-NEXT: li a2, 192
; RV32IMB-NEXT: mulhu a2, a0, a2
; RV32IMB-NEXT: sh1add a1, a1, a1
; RV32IMB-NEXT: slli a1, a1, 6
Expand Down Expand Up @@ -343,14 +343,14 @@ define i32 @add_mul_combine_reject_e1(i32 %x) {
; RV32IMB-LABEL: add_mul_combine_reject_e1:
; RV32IMB: # %bb.0:
; RV32IMB-NEXT: addi a0, a0, 1971
; RV32IMB-NEXT: addi a1, zero, 29
; RV32IMB-NEXT: li a1, 29
; RV32IMB-NEXT: mul a0, a0, a1
; RV32IMB-NEXT: ret
;
; RV64IMB-LABEL: add_mul_combine_reject_e1:
; RV64IMB: # %bb.0:
; RV64IMB-NEXT: addiw a0, a0, 1971
; RV64IMB-NEXT: addi a1, zero, 29
; RV64IMB-NEXT: li a1, 29
; RV64IMB-NEXT: mulw a0, a0, a1
; RV64IMB-NEXT: ret
%tmp0 = mul i32 %x, 29
Expand All @@ -362,14 +362,14 @@ define signext i32 @add_mul_combine_reject_e2(i32 signext %x) {
; RV32IMB-LABEL: add_mul_combine_reject_e2:
; RV32IMB: # %bb.0:
; RV32IMB-NEXT: addi a0, a0, 1971
; RV32IMB-NEXT: addi a1, zero, 29
; RV32IMB-NEXT: li a1, 29
; RV32IMB-NEXT: mul a0, a0, a1
; RV32IMB-NEXT: ret
;
; RV64IMB-LABEL: add_mul_combine_reject_e2:
; RV64IMB: # %bb.0:
; RV64IMB-NEXT: addiw a0, a0, 1971
; RV64IMB-NEXT: addi a1, zero, 29
; RV64IMB-NEXT: li a1, 29
; RV64IMB-NEXT: mulw a0, a0, a1
; RV64IMB-NEXT: ret
%tmp0 = mul i32 %x, 29
Expand All @@ -380,7 +380,7 @@ define signext i32 @add_mul_combine_reject_e2(i32 signext %x) {
define i64 @add_mul_combine_reject_e3(i64 %x) {
; RV32IMB-LABEL: add_mul_combine_reject_e3:
; RV32IMB: # %bb.0:
; RV32IMB-NEXT: addi a2, zero, 29
; RV32IMB-NEXT: li a2, 29
; RV32IMB-NEXT: mul a1, a1, a2
; RV32IMB-NEXT: mulhu a3, a0, a2
; RV32IMB-NEXT: add a1, a3, a1
Expand All @@ -395,7 +395,7 @@ define i64 @add_mul_combine_reject_e3(i64 %x) {
; RV64IMB-LABEL: add_mul_combine_reject_e3:
; RV64IMB: # %bb.0:
; RV64IMB-NEXT: addi a0, a0, 1971
; RV64IMB-NEXT: addi a1, zero, 29
; RV64IMB-NEXT: li a1, 29
; RV64IMB-NEXT: mul a0, a0, a1
; RV64IMB-NEXT: ret
%tmp0 = mul i64 %x, 29
Expand All @@ -407,15 +407,15 @@ define i32 @add_mul_combine_reject_f1(i32 %x) {
; RV32IMB-LABEL: add_mul_combine_reject_f1:
; RV32IMB: # %bb.0:
; RV32IMB-NEXT: addi a0, a0, 1972
; RV32IMB-NEXT: addi a1, zero, 29
; RV32IMB-NEXT: li a1, 29
; RV32IMB-NEXT: mul a0, a0, a1
; RV32IMB-NEXT: addi a0, a0, 11
; RV32IMB-NEXT: ret
;
; RV64IMB-LABEL: add_mul_combine_reject_f1:
; RV64IMB: # %bb.0:
; RV64IMB-NEXT: addiw a0, a0, 1972
; RV64IMB-NEXT: addi a1, zero, 29
; RV64IMB-NEXT: li a1, 29
; RV64IMB-NEXT: mulw a0, a0, a1
; RV64IMB-NEXT: addiw a0, a0, 11
; RV64IMB-NEXT: ret
Expand All @@ -428,15 +428,15 @@ define signext i32 @add_mul_combine_reject_f2(i32 signext %x) {
; RV32IMB-LABEL: add_mul_combine_reject_f2:
; RV32IMB: # %bb.0:
; RV32IMB-NEXT: addi a0, a0, 1972
; RV32IMB-NEXT: addi a1, zero, 29
; RV32IMB-NEXT: li a1, 29
; RV32IMB-NEXT: mul a0, a0, a1
; RV32IMB-NEXT: addi a0, a0, 11
; RV32IMB-NEXT: ret
;
; RV64IMB-LABEL: add_mul_combine_reject_f2:
; RV64IMB: # %bb.0:
; RV64IMB-NEXT: addiw a0, a0, 1972
; RV64IMB-NEXT: addi a1, zero, 29
; RV64IMB-NEXT: li a1, 29
; RV64IMB-NEXT: mulw a0, a0, a1
; RV64IMB-NEXT: addiw a0, a0, 11
; RV64IMB-NEXT: ret
Expand All @@ -448,7 +448,7 @@ define signext i32 @add_mul_combine_reject_f2(i32 signext %x) {
define i64 @add_mul_combine_reject_f3(i64 %x) {
; RV32IMB-LABEL: add_mul_combine_reject_f3:
; RV32IMB: # %bb.0:
; RV32IMB-NEXT: addi a2, zero, 29
; RV32IMB-NEXT: li a2, 29
; RV32IMB-NEXT: mul a1, a1, a2
; RV32IMB-NEXT: mulhu a3, a0, a2
; RV32IMB-NEXT: add a1, a3, a1
Expand All @@ -463,7 +463,7 @@ define i64 @add_mul_combine_reject_f3(i64 %x) {
; RV64IMB-LABEL: add_mul_combine_reject_f3:
; RV64IMB: # %bb.0:
; RV64IMB-NEXT: addi a0, a0, 1972
; RV64IMB-NEXT: addi a1, zero, 29
; RV64IMB-NEXT: li a1, 29
; RV64IMB-NEXT: mul a0, a0, a1
; RV64IMB-NEXT: addi a0, a0, 11
; RV64IMB-NEXT: ret
Expand Down Expand Up @@ -517,7 +517,7 @@ define signext i32 @add_mul_combine_reject_g2(i32 signext %x) {
define i64 @add_mul_combine_reject_g3(i64 %x) {
; RV32IMB-LABEL: add_mul_combine_reject_g3:
; RV32IMB: # %bb.0:
; RV32IMB-NEXT: addi a2, zero, 73
; RV32IMB-NEXT: li a2, 73
; RV32IMB-NEXT: mul a1, a1, a2
; RV32IMB-NEXT: mulhu a3, a0, a2
; RV32IMB-NEXT: add a1, a3, a1
Expand Down Expand Up @@ -545,7 +545,7 @@ define i64 @add_mul_combine_reject_g3(i64 %x) {
define i64 @add_mul_combine_infinite_loop(i64 %x) {
; RV32IMB-LABEL: add_mul_combine_infinite_loop:
; RV32IMB: # %bb.0:
; RV32IMB-NEXT: addi a2, zero, 24
; RV32IMB-NEXT: li a2, 24
; RV32IMB-NEXT: mulhu a2, a0, a2
; RV32IMB-NEXT: sh1add a1, a1, a1
; RV32IMB-NEXT: sh3add a1, a1, a2
Expand All @@ -561,7 +561,7 @@ define i64 @add_mul_combine_infinite_loop(i64 %x) {
; RV64IMB: # %bb.0:
; RV64IMB-NEXT: addi a0, a0, 86
; RV64IMB-NEXT: sh1add a0, a0, a0
; RV64IMB-NEXT: addi a1, zero, -16
; RV64IMB-NEXT: li a1, -16
; RV64IMB-NEXT: sh3add a0, a0, a1
; RV64IMB-NEXT: ret
%tmp0 = mul i64 %x, 24
Expand Down
22 changes: 11 additions & 11 deletions llvm/test/CodeGen/RISCV/alloca.ll
View file
Expand Up @@ -76,20 +76,20 @@ define void @alloca_callframe(i32 %n) nounwind {
; RV32I-NEXT: sub a0, sp, a0
; RV32I-NEXT: mv sp, a0
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: addi a1, zero, 12
; RV32I-NEXT: li a1, 12
; RV32I-NEXT: sw a1, 12(sp)
; RV32I-NEXT: addi a1, zero, 11
; RV32I-NEXT: li a1, 11
; RV32I-NEXT: sw a1, 8(sp)
; RV32I-NEXT: addi a1, zero, 10
; RV32I-NEXT: li a1, 10
; RV32I-NEXT: sw a1, 4(sp)
; RV32I-NEXT: addi t0, zero, 9
; RV32I-NEXT: addi a1, zero, 2
; RV32I-NEXT: addi a2, zero, 3
; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: addi a5, zero, 6
; RV32I-NEXT: addi a6, zero, 7
; RV32I-NEXT: addi a7, zero, 8
; RV32I-NEXT: li t0, 9
; RV32I-NEXT: li a1, 2
; RV32I-NEXT: li a2, 3
; RV32I-NEXT: li a3, 4
; RV32I-NEXT: li a4, 5
; RV32I-NEXT: li a5, 6
; RV32I-NEXT: li a6, 7
; RV32I-NEXT: li a7, 8
; RV32I-NEXT: sw t0, 0(sp)
; RV32I-NEXT: call func@plt
; RV32I-NEXT: addi sp, sp, 16
Expand Down
12 changes: 6 additions & 6 deletions llvm/test/CodeGen/RISCV/alu32.ll
View file
Expand Up @@ -192,13 +192,13 @@ define i32 @sub(i32 %a, i32 %b) nounwind {
define i32 @sub_negative_constant_lhs(i32 %a) nounwind {
; RV32I-LABEL: sub_negative_constant_lhs:
; RV32I: # %bb.0:
; RV32I-NEXT: addi a1, zero, -2
; RV32I-NEXT: li a1, -2
; RV32I-NEXT: sub a0, a1, a0
; RV32I-NEXT: ret
;
; RV64I-LABEL: sub_negative_constant_lhs:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a1, zero, -2
; RV64I-NEXT: li a1, -2
; RV64I-NEXT: subw a0, a1, a0
; RV64I-NEXT: ret
%1 = sub i32 -2, %a
Expand All @@ -222,13 +222,13 @@ define i32 @sll(i32 %a, i32 %b) nounwind {
define i32 @sll_negative_constant_lhs(i32 %a) nounwind {
; RV32I-LABEL: sll_negative_constant_lhs:
; RV32I: # %bb.0:
; RV32I-NEXT: addi a1, zero, -1
; RV32I-NEXT: li a1, -1
; RV32I-NEXT: sll a0, a1, a0
; RV32I-NEXT: ret
;
; RV64I-LABEL: sll_negative_constant_lhs:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a1, zero, -1
; RV64I-NEXT: li a1, -1
; RV64I-NEXT: sllw a0, a1, a0
; RV64I-NEXT: ret
%1 = shl i32 -1, %a
Expand Down Expand Up @@ -300,13 +300,13 @@ define i32 @srl(i32 %a, i32 %b) nounwind {
define i32 @srl_negative_constant_lhs(i32 %a) nounwind {
; RV32I-LABEL: srl_negative_constant_lhs:
; RV32I: # %bb.0:
; RV32I-NEXT: addi a1, zero, -1
; RV32I-NEXT: li a1, -1
; RV32I-NEXT: srl a0, a1, a0
; RV32I-NEXT: ret
;
; RV64I-LABEL: srl_negative_constant_lhs:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a1, zero, -1
; RV64I-NEXT: li a1, -1
; RV64I-NEXT: srlw a0, a1, a0
; RV64I-NEXT: ret
%1 = lshr i32 -1, %a
Expand Down

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