[LoongArch][test] (6/6) Add encoding and mnemonics tests

With the benefit of D88392, instruction encoding and mnemonic testing can be achieved within MIR files before AsmParser is ready. This patch adds such tests which cover all basic integer instructions we defined in previous patch. Similarly those tests will be rewrote by .s and moved to test/MC/LoongArch. Differential revision: https://reviews.llvm.org/D115862
llvm · Feb 10, 2022 · af3bc0d · af3bc0d
1 parent 6caee48
commit af3bc0d
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diff --git a/llvm/test/CodeGen/LoongArch/1ri.mir b/llvm/test/CodeGen/LoongArch/1ri.mir
@@ -0,0 +1,96 @@
+# RUN: llc %s -mtriple=loongarch64 -start-after=prologepilog -O0 -filetype=obj -o - \
+# RUN:   | extract-section .text \
+# RUN:   | FileCheck %s -check-prefix=CHECK-ENC
+# RUN: llc %s -mtriple=loongarch64 -start-after=prologepilog -O0 -filetype=asm -o - \
+# RUN:   | FileCheck %s -check-prefix=CHECK-ASM
+
+# -------------------------------------------------------------------------------------------------
+#                                           Encoding format: 1RI20
+# -------------------------------------------------------------------------------------------------
+# ---------------------+-----------------------------------------------------------+---------------
+#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
+# ---------------------+-----------------------------------------------------------+---------------
+#        opcode        |                       imm20                               |      rd
+# ---------------------+-----------------------------------------------------------+---------------
+
+---
+# CHECK-LABEL: test_LU12I_W:
+# CHECK-ENC: 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 1 0 0
+# CHECK-ASM: lu12i.w	a0, 49
+name: test_LU12I_W
+body: |
+  bb.0:
+    $r4 = LU12I_W 49
+...
+---
+# CHECK-LABEL: test_LU32I_D:
+# CHECK-ENC: 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0
+# CHECK-ASM: lu32i.d	a0, 196
+name: test_LU32I_D
+body: |
+  bb.0:
+    $r4 = LU32I_D 196
+...
+---
+# CHECK-LABEL: test_PCADDI:
+# CHECK-ENC: 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 1 1 0 0 1 0 0
+# CHECK-ASM: pcaddi	a0, 187
+name: test_PCADDI
+body: |
+  bb.0:
+    $r4 = PCADDI 187
+...
+---
+# CHECK-LABEL: test_PCALAU12I:
+# CHECK-ENC: 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 1 0 0 1 0 0
+# CHECK-ASM: pcalau12i	a0, 89
+name: test_PCALAU12I
+body: |
+  bb.0:
+    $r4 = PCALAU12I 89
+...
+---
+# CHECK-LABEL: test_PCADDU12I:
+# CHECK-ENC: 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0
+# CHECK-ASM: pcaddu12i	a0, 37
+name: test_PCADDU12I
+body: |
+  bb.0:
+    $r4 = PCADDU12I 37
+...
+---
+# CHECK-LABEL: test_PCADDU18I:
+# CHECK-ENC: 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 1 0 0
+# CHECK-ASM: pcaddu18i	a0, 26
+name: test_PCADDU18I
+body: |
+  bb.0:
+    $r4 = PCADDU18I 26
+...
+
+# -------------------------------------------------------------------------------------------------
+#                                           Encoding format: 1RI21
+# -------------------------------------------------------------------------------------------------
+# ------------------+-----------------------------------------------+--------------+---------------
+#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
+# ------------------+-----------------------------------------------+--------------+---------------
+#      opcode       |                    imm21{15-0}                |      rj      | imm21{20-16}
+# ------------------+-----------------------------------------------+--------------+---------------
+
+---
+# CHECK-LABEL: test_BEQZ:
+# CHECK-ENC: 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 0 1 0 0 0 0 0 0 0
+# CHECK-ASM: beqz	a0, 23
+name: test_BEQZ
+body: |
+  bb.0:
+    BEQZ $r4, 23
+...
+---
+# CHECK-LABEL: test_BNEZ:
+# CHECK-ENC: 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 0 0 0 0 0 0
+# CHECK-ASM: bnez	a0, 21
+name: test_BNEZ
+body: |
+  bb.0:
+    BNEZ $r4, 21
diff --git a/llvm/test/CodeGen/LoongArch/2r.mir b/llvm/test/CodeGen/LoongArch/2r.mir
@@ -0,0 +1,230 @@
+# RUN: llc %s -mtriple=loongarch64 -start-after=prologepilog -O0 -filetype=obj -o - \
+# RUN:   | extract-section .text \
+# RUN:   | FileCheck %s -check-prefix=CHECK-ENC
+# RUN: llc %s -mtriple=loongarch64 -start-after=prologepilog -O0 -filetype=asm -o - \
+# RUN:   | FileCheck %s -check-prefix=CHECK-ASM
+
+# -------------------------------------------------------------------------------------------------
+#                                           Encoding format: 2R
+# -------------------------------------------------------------------------------------------------
+# ------------------------------------------------------------------+--------------+---------------
+#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
+# ------------------------------------------------------------------+--------------+---------------
+#                           opcode                                  |      rj      |      rd
+# ------------------------------------------------------------------+--------------+---------------
+
+---
+# CHECK-LABEL: test_CLO_W:
+# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0
+# CHECK-ASM: clo.w	a0, a1
+name: test_CLO_W
+body: |
+  bb.0:
+    $r4 = CLO_W $r5
+...
+---
+# CHECK-LABEL: test_CLZ_W:
+# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 1 0 0 1 0 0
+# CHECK-ASM: clz.w	a0, a1
+name: test_CLZ_W
+body: |
+  bb.0:
+    $r4 = CLZ_W $r5
+...
+---
+# CHECK-LABEL: test_CTO_W:
+# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
+# CHECK-ASM: cto.w	a0, a1
+name: test_CTO_W
+body: |
+  bb.0:
+    $r4 = CTO_W $r5
+...
+---
+# CHECK-LABEL: test_CTZ_W:
+# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 0 1 0 0 1 0 0
+# CHECK-ASM: ctz.w	a0, a1
+name: test_CTZ_W
+body: |
+  bb.0:
+    $r4 = CTZ_W $r5
+...
+---
+# CHECK-LABEL: test_CLO_D:
+# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 1 0 0
+# CHECK-ASM: clo.d	a0, a1
+name: test_CLO_D
+body: |
+  bb.0:
+    $r4 = CLO_D $r5
+...
+---
+# CHECK-LABEL: test_CLZ_D:
+# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 1 0 0 1 0 0
+# CHECK-ASM: clz.d	a0, a1
+name: test_CLZ_D
+body: |
+  bb.0:
+    $r4 = CLZ_D $r5
+...
+---
+# CHECK-LABEL: test_CTO_D:
+# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 1 0 0 1 0 0
+# CHECK-ASM: cto.d	a0, a1
+name: test_CTO_D
+body: |
+  bb.0:
+    $r4 = CTO_D $r5
+...
+---
+# CHECK-LABEL: test_CTZ_D:
+# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0
+# CHECK-ASM: ctz.d	a0, a1
+name: test_CTZ_D
+body: |
+  bb.0:
+    $r4 = CTZ_D $r5
+...
+---
+# CHECK-LABEL: test_REVB_2H:
+# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0 1 0 0 1 0 0
+# CHECK-ASM: revb.2h	a0, a1
+name: test_REVB_2H
+body: |
+  bb.0:
+    $r4 = REVB_2H $r5
+...
+---
+# CHECK-LABEL: test_REVB_4H:
+# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 1 0 1 0 0 1 0 0
+# CHECK-ASM: revb.4h	a0, a1
+name: test_REVB_4H
+body: |
+  bb.0:
+    $r4 = REVB_4H $r5
+...
+---
+# CHECK-LABEL: test_REVB_2W:
+# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 1 0 1 0 0 1 0 0
+# CHECK-ASM: revb.2w	a0, a1
+name: test_REVB_2W
+body: |
+  bb.0:
+    $r4 = REVB_2W $r5
+...
+---
+# CHECK-LABEL: test_REVB_D:
+# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 0 1 0 0 1 0 0
+# CHECK-ASM: revb.d	a0, a1
+name: test_REVB_D
+body: |
+  bb.0:
+    $r4 = REVB_D $r5
+...
+---
+# CHECK-LABEL: test_REVH_2W:
+# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 1 0 0 1 0 0
+# CHECK-ASM: revh.2w	a0, a1
+name: test_REVH_2W
+body: |
+  bb.0:
+    $r4 = REVH_2W $r5
+...
+---
+# CHECK-LABEL: test_REVH_D:
+# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 1 0 0 1 0 0
+# CHECK-ASM: revh.d	a0, a1
+name: test_REVH_D
+body: |
+  bb.0:
+    $r4 = REVH_D $r5
+...
+---
+# CHECK-LABEL: test_BITREV_4B:
+# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 0 1 0 0 1 0 0
+# CHECK-ASM: bitrev.4b	a0, a1
+name: test_BITREV_4B
+body: |
+  bb.0:
+    $r4 = BITREV_4B $r5
+...
+---
+# CHECK-LABEL: test_BITREV_8B:
+# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 0 1 0 0
+# CHECK-ASM: bitrev.8b	a0, a1
+name: test_BITREV_8B
+body: |
+  bb.0:
+    $r4 = BITREV_8B $r5
+...
+---
+# CHECK-LABEL: test_BITREV_W:
+# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 0
+# CHECK-ASM: bitrev.w	a0, a1
+name: test_BITREV_W
+body: |
+  bb.0:
+    $r4 = BITREV_W $r5
+...
+---
+# CHECK-LABEL: test_BITREV_D:
+# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 0 0 1 0 0
+# CHECK-ASM: bitrev.d	a0, a1
+name: test_BITREV_D
+body: |
+  bb.0:
+    $r4 = BITREV_D $r5
+...
+---
+# CHECK-LABEL: test_EXT_W_H:
+# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 1 0 1 0 0 1 0 0
+# CHECK-ASM: ext.w.h	a0, a1
+name: test_EXT_W_H
+body: |
+  bb.0:
+    $r4 = EXT_W_H $r5
+...
+---
+# CHECK-LABEL: test_EXT_W_B:
+# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 0 1 0 1 0 0 1 0 0
+# CHECK-ASM: ext.w.b	a0, a1
+name: test_EXT_W_B
+body: |
+  bb.0:
+    $r4 = EXT_W_B $r5
+...
+---
+# CHECK-LABEL: test_CPUCFG:
+# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 0 1 0 1 0 0 1 0 0
+# CHECK-ASM: cpucfg	a0, a1
+name: test_CPUCFG
+body: |
+  bb.0:
+    $r4 = CPUCFG $r5
+...
+---
+# CHECK-LABEL: test_RDTIMEL_W:
+# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 1 0 0 1 0 0
+# CHECK-ASM: rdtimel.w	a0, a1
+name: test_RDTIMEL_W
+body: |
+  bb.0:
+    $r4, $r5 = RDTIMEL_W
+...
+---
+# CHECK-LABEL: test_RDTIMEH_W:
+# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 1 0 1 0 0 1 0 0
+# CHECK-ASM: rdtimeh.w	a0, a1
+name: test_RDTIMEH_W
+body: |
+  bb.0:
+    $r4, $r5 = RDTIMEH_W
+...
+---
+# CHECK-LABEL: test_RDTIME_D:
+# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 1 0 1 0 0 1 0 0
+# CHECK-ASM: rdtime.d	a0, a1
+name: test_RDTIME_D
+body: |
+  bb.0:
+    $r4, $r5 = RDTIME_D