ARMFrameLowering.cpp - fix MSVC "result of 32-bit shift implicitly co…

…nverted to 64 bits" warning. NFC.
llvm · Mar 31, 2023 · b206145 · b206145
1 parent bd20a34
commit b206145
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/llvm/lib/Target/ARM/ARMFrameLowering.cpp b/llvm/lib/Target/ARM/ARMFrameLowering.cpp
@@ -363,7 +363,7 @@ static MachineBasicBlock::iterator insertSEH(MachineBasicBlock::iterator MBBI,
         MBBI->getOperand(3).getImm() == -4) {
       unsigned Reg = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg());
       MIB = BuildMI(MF, DL, TII.get(ARM::SEH_SaveRegs))
-                .addImm(1 << Reg)
+                .addImm(1ULL << Reg)
                 .addImm(/*Wide=*/1)
                 .setMIFlags(Flags);
     } else {
@@ -377,7 +377,7 @@ static MachineBasicBlock::iterator insertSEH(MachineBasicBlock::iterator MBBI,
         MBBI->getOperand(3).getImm() == 4) {
       unsigned Reg = RegInfo->getSEHRegNum(MBBI->getOperand(0).getReg());
       MIB = BuildMI(MF, DL, TII.get(ARM::SEH_SaveRegs))
-                .addImm(1 << Reg)
+                .addImm(1ULL << Reg)
                 .addImm(/*Wide=*/1)
                 .setMIFlags(Flags);
     } else {