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[AArch64][GlobalISel] Add selection tests for vector G_UMULH/G_SMULH.
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We already import these patterns from SelectionDAG.
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@aemerson
aemerson committed Sep 29, 2021
1 parent 8f9f959 commit b2b122d
Showing 1 changed file with 187 additions and 3 deletions.
190 changes: 187 additions & 3 deletions llvm/test/CodeGen/AArch64/GlobalISel/select-mul.mir
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Expand Up @@ -21,14 +21,198 @@ body: |
; (SMADDLrrr GPR32:$Rn, (MOVi32imm (trunc_imm imm:$C)), XZR)>;
; CHECK-LABEL: name: mul_i64_sext_imm32
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 3
; CHECK: [[SMADDLrrr:%[0-9]+]]:gpr64 = SMADDLrrr [[COPY]], [[MOVi32imm]], $xzr
; CHECK: $x0 = COPY [[SMADDLrrr]]
; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 3
; CHECK-NEXT: [[SMADDLrrr:%[0-9]+]]:gpr64 = SMADDLrrr [[COPY]], [[MOVi32imm]], $xzr
; CHECK-NEXT: $x0 = COPY [[SMADDLrrr]]
%0:gpr(s32) = COPY $w0
%1:gpr(s64) = G_SEXT %0(s32)
%2:gpr(s64) = G_CONSTANT i64 3
%3:gpr(s64) = G_MUL %1, %2
$x0 = COPY %3(s64)
...
---
name: umulh_v8s16
legalized: true
regBankSelected: true
exposesReturnsTwice: false
tracksRegLiveness: true
liveins:
- { reg: '$q0', virtual-reg: '' }
body: |
bb.1:
liveins: $q0, $q1
; CHECK-LABEL: name: umulh_v8s16
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
; CHECK-NEXT: [[UMULLv8i16_v4i32_:%[0-9]+]]:fpr128 = UMULLv8i16_v4i32 [[COPY]], [[COPY1]]
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[COPY1]].dsub
; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr64 = COPY [[COPY]].dsub
; CHECK-NEXT: [[UMULLv4i16_v4i32_:%[0-9]+]]:fpr128 = UMULLv4i16_v4i32 [[COPY3]], [[COPY2]]
; CHECK-NEXT: %mul:fpr128 = UZP2v8i16 [[UMULLv4i16_v4i32_]], [[UMULLv8i16_v4i32_]]
; CHECK-NEXT: $q0 = COPY %mul
; CHECK-NEXT: RET_ReallyLR implicit $q0
%0:fpr(<8 x s16>) = COPY $q0
%1:fpr(<8 x s16>) = COPY $q1
%mul:fpr(<8 x s16>) = G_UMULH %0, %1
$q0 = COPY %mul(<8 x s16>)
RET_ReallyLR implicit $q0
...
---
name: umulh_v16s8
legalized: true
regBankSelected: true
exposesReturnsTwice: false
tracksRegLiveness: true
liveins:
- { reg: '$q0', virtual-reg: '' }
body: |
bb.1:
liveins: $q0, $q1
; CHECK-LABEL: name: umulh_v16s8
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
; CHECK-NEXT: [[UMULLv16i8_v8i16_:%[0-9]+]]:fpr128 = UMULLv16i8_v8i16 [[COPY]], [[COPY1]]
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[COPY1]].dsub
; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr64 = COPY [[COPY]].dsub
; CHECK-NEXT: [[UMULLv8i8_v8i16_:%[0-9]+]]:fpr128 = UMULLv8i8_v8i16 [[COPY3]], [[COPY2]]
; CHECK-NEXT: %mul:fpr128 = UZP2v16i8 [[UMULLv8i8_v8i16_]], [[UMULLv16i8_v8i16_]]
; CHECK-NEXT: $q0 = COPY %mul
; CHECK-NEXT: RET_ReallyLR implicit $q0
%0:fpr(<16 x s8>) = COPY $q0
%1:fpr(<16 x s8>) = COPY $q1
%mul:fpr(<16 x s8>) = G_UMULH %0, %1
$q0 = COPY %mul(<16 x s8>)
RET_ReallyLR implicit $q0
...
---
name: umulh_v4s32
legalized: true
regBankSelected: true
exposesReturnsTwice: false
tracksRegLiveness: true
liveins:
- { reg: '$q0', virtual-reg: '' }
body: |
bb.1:
liveins: $q0, $q1
; CHECK-LABEL: name: umulh_v4s32
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
; CHECK-NEXT: [[UMULLv4i32_v2i64_:%[0-9]+]]:fpr128 = UMULLv4i32_v2i64 [[COPY]], [[COPY1]]
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[COPY1]].dsub
; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr64 = COPY [[COPY]].dsub
; CHECK-NEXT: [[UMULLv2i32_v2i64_:%[0-9]+]]:fpr128 = UMULLv2i32_v2i64 [[COPY3]], [[COPY2]]
; CHECK-NEXT: %mul:fpr128 = UZP2v4i32 [[UMULLv2i32_v2i64_]], [[UMULLv4i32_v2i64_]]
; CHECK-NEXT: $q0 = COPY %mul
; CHECK-NEXT: RET_ReallyLR implicit $q0
%0:fpr(<4 x s32>) = COPY $q0
%1:fpr(<4 x s32>) = COPY $q1
%mul:fpr(<4 x s32>) = G_UMULH %0, %1
$q0 = COPY %mul(<4 x s32>)
RET_ReallyLR implicit $q0
...
---
name: smulh_v8s16
legalized: true
regBankSelected: true
exposesReturnsTwice: false
tracksRegLiveness: true
liveins:
- { reg: '$q0', virtual-reg: '' }
body: |
bb.1:
liveins: $q0, $q1
; CHECK-LABEL: name: smulh_v8s16
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
; CHECK-NEXT: [[SMULLv8i16_v4i32_:%[0-9]+]]:fpr128 = SMULLv8i16_v4i32 [[COPY]], [[COPY1]]
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[COPY1]].dsub
; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr64 = COPY [[COPY]].dsub
; CHECK-NEXT: [[SMULLv4i16_v4i32_:%[0-9]+]]:fpr128 = SMULLv4i16_v4i32 [[COPY3]], [[COPY2]]
; CHECK-NEXT: %mul:fpr128 = UZP2v8i16 [[SMULLv4i16_v4i32_]], [[SMULLv8i16_v4i32_]]
; CHECK-NEXT: $q0 = COPY %mul
; CHECK-NEXT: RET_ReallyLR implicit $q0
%0:fpr(<8 x s16>) = COPY $q0
%1:fpr(<8 x s16>) = COPY $q1
%mul:fpr(<8 x s16>) = G_SMULH %0, %1
$q0 = COPY %mul(<8 x s16>)
RET_ReallyLR implicit $q0
...
---
name: smulh_v16s8
legalized: true
regBankSelected: true
exposesReturnsTwice: false
tracksRegLiveness: true
liveins:
- { reg: '$q0', virtual-reg: '' }
body: |
bb.1:
liveins: $q0, $q1
; CHECK-LABEL: name: smulh_v16s8
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
; CHECK-NEXT: [[SMULLv16i8_v8i16_:%[0-9]+]]:fpr128 = SMULLv16i8_v8i16 [[COPY]], [[COPY1]]
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[COPY1]].dsub
; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr64 = COPY [[COPY]].dsub
; CHECK-NEXT: [[SMULLv8i8_v8i16_:%[0-9]+]]:fpr128 = SMULLv8i8_v8i16 [[COPY3]], [[COPY2]]
; CHECK-NEXT: %mul:fpr128 = UZP2v16i8 [[SMULLv8i8_v8i16_]], [[SMULLv16i8_v8i16_]]
; CHECK-NEXT: $q0 = COPY %mul
; CHECK-NEXT: RET_ReallyLR implicit $q0
%0:fpr(<16 x s8>) = COPY $q0
%1:fpr(<16 x s8>) = COPY $q1
%mul:fpr(<16 x s8>) = G_SMULH %0, %1
$q0 = COPY %mul(<16 x s8>)
RET_ReallyLR implicit $q0
...
---
name: smulh_v4s32
legalized: true
regBankSelected: true
exposesReturnsTwice: false
tracksRegLiveness: true
liveins:
- { reg: '$q0', virtual-reg: '' }
body: |
bb.1:
liveins: $q0, $q1
; CHECK-LABEL: name: smulh_v4s32
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
; CHECK-NEXT: [[SMULLv4i32_v2i64_:%[0-9]+]]:fpr128 = SMULLv4i32_v2i64 [[COPY]], [[COPY1]]
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[COPY1]].dsub
; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr64 = COPY [[COPY]].dsub
; CHECK-NEXT: [[SMULLv2i32_v2i64_:%[0-9]+]]:fpr128 = SMULLv2i32_v2i64 [[COPY3]], [[COPY2]]
; CHECK-NEXT: %mul:fpr128 = UZP2v4i32 [[SMULLv2i32_v2i64_]], [[SMULLv4i32_v2i64_]]
; CHECK-NEXT: $q0 = COPY %mul
; CHECK-NEXT: RET_ReallyLR implicit $q0
%0:fpr(<4 x s32>) = COPY $q0
%1:fpr(<4 x s32>) = COPY $q1
%mul:fpr(<4 x s32>) = G_SMULH %0, %1
$q0 = COPY %mul(<4 x s32>)
RET_ReallyLR implicit $q0
...

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