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[RISCV] Add test cases that show failure to use some W instructions i…
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…f they are proceeded by a load. NFC

The loads end up becoming sextload/zextload which prevent our
isel patterns from finding the sign_extend_inreg or AND instruction
we need.

The easiest way to fix this is to use computeKnownBits or
ComputeNumSignBits in our isel matching to catch this.
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@topperc
topperc committed Jun 10, 2021
1 parent ffaca14 commit b35a842
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Showing 4 changed files with 344 additions and 140 deletions.
170 changes: 108 additions & 62 deletions llvm/test/CodeGen/RISCV/double-convert.ll
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Expand Up @@ -191,6 +191,29 @@ define double @fcvt_d_w(i32 %a) nounwind {
ret double %1
}

define double @fcvt_d_w_load(i32* %p) nounwind {
; RV32IFD-LABEL: fcvt_d_w_load:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: lw a0, 0(a0)
; RV32IFD-NEXT: fcvt.d.w ft0, a0
; RV32IFD-NEXT: fsd ft0, 8(sp)
; RV32IFD-NEXT: lw a0, 8(sp)
; RV32IFD-NEXT: lw a1, 12(sp)
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: fcvt_d_w_load:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: lw a0, 0(a0)
; RV64IFD-NEXT: fcvt.d.l ft0, a0
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret
%a = load i32, i32* %p
%1 = sitofp i32 %a to double
ret double %1
}

define double @fcvt_d_wu(i32 %a) nounwind {
; RV32IFD-LABEL: fcvt_d_wu:
; RV32IFD: # %bb.0:
Expand All @@ -211,6 +234,29 @@ define double @fcvt_d_wu(i32 %a) nounwind {
ret double %1
}

define double @fcvt_d_wu_load(i32* %p) nounwind {
; RV32IFD-LABEL: fcvt_d_wu_load:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: lw a0, 0(a0)
; RV32IFD-NEXT: fcvt.d.wu ft0, a0
; RV32IFD-NEXT: fsd ft0, 8(sp)
; RV32IFD-NEXT: lw a0, 8(sp)
; RV32IFD-NEXT: lw a1, 12(sp)
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: fcvt_d_wu_load:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: lwu a0, 0(a0)
; RV64IFD-NEXT: fcvt.d.lu ft0, a0
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret
%a = load i32, i32* %p
%1 = uitofp i32 %a to double
ret double %1
}

define i64 @fcvt_l_d(double %a) nounwind {
; RV32IFD-LABEL: fcvt_l_d:
; RV32IFD: # %bb.0:
Expand Down Expand Up @@ -241,79 +287,79 @@ define i64 @fcvt_l_d_sat(double %a) nounwind {
; RV32IFD-NEXT: fsd ft0, 8(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: call __fixdfdi@plt
; RV32IFD-NEXT: fld ft1, 8(sp) # 8-byte Folded Reload
; RV32IFD-NEXT: lui a2, %hi(.LCPI9_0)
; RV32IFD-NEXT: fld ft0, %lo(.LCPI9_0)(a2)
; RV32IFD-NEXT: lui a2, %hi(.LCPI11_0)
; RV32IFD-NEXT: fld ft0, %lo(.LCPI11_0)(a2)
; RV32IFD-NEXT: fle.d a3, ft0, ft1
; RV32IFD-NEXT: mv a2, a0
; RV32IFD-NEXT: bnez a3, .LBB9_2
; RV32IFD-NEXT: bnez a3, .LBB11_2
; RV32IFD-NEXT: # %bb.1: # %start
; RV32IFD-NEXT: mv a2, zero
; RV32IFD-NEXT: .LBB9_2: # %start
; RV32IFD-NEXT: lui a0, %hi(.LCPI9_1)
; RV32IFD-NEXT: fld ft0, %lo(.LCPI9_1)(a0)
; RV32IFD-NEXT: .LBB11_2: # %start
; RV32IFD-NEXT: lui a0, %hi(.LCPI11_1)
; RV32IFD-NEXT: fld ft0, %lo(.LCPI11_1)(a0)
; RV32IFD-NEXT: flt.d a4, ft0, ft1
; RV32IFD-NEXT: addi a0, zero, -1
; RV32IFD-NEXT: beqz a4, .LBB9_9
; RV32IFD-NEXT: beqz a4, .LBB11_9
; RV32IFD-NEXT: # %bb.3: # %start
; RV32IFD-NEXT: feq.d a2, ft1, ft1
; RV32IFD-NEXT: beqz a2, .LBB9_10
; RV32IFD-NEXT: .LBB9_4: # %start
; RV32IFD-NEXT: beqz a2, .LBB11_10
; RV32IFD-NEXT: .LBB11_4: # %start
; RV32IFD-NEXT: lui a5, 524288
; RV32IFD-NEXT: beqz a3, .LBB9_11
; RV32IFD-NEXT: .LBB9_5: # %start
; RV32IFD-NEXT: bnez a4, .LBB9_12
; RV32IFD-NEXT: .LBB9_6: # %start
; RV32IFD-NEXT: bnez a2, .LBB9_8
; RV32IFD-NEXT: .LBB9_7: # %start
; RV32IFD-NEXT: beqz a3, .LBB11_11
; RV32IFD-NEXT: .LBB11_5: # %start
; RV32IFD-NEXT: bnez a4, .LBB11_12
; RV32IFD-NEXT: .LBB11_6: # %start
; RV32IFD-NEXT: bnez a2, .LBB11_8
; RV32IFD-NEXT: .LBB11_7: # %start
; RV32IFD-NEXT: mv a1, zero
; RV32IFD-NEXT: .LBB9_8: # %start
; RV32IFD-NEXT: .LBB11_8: # %start
; RV32IFD-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 32
; RV32IFD-NEXT: ret
; RV32IFD-NEXT: .LBB9_9: # %start
; RV32IFD-NEXT: .LBB11_9: # %start
; RV32IFD-NEXT: mv a0, a2
; RV32IFD-NEXT: feq.d a2, ft1, ft1
; RV32IFD-NEXT: bnez a2, .LBB9_4
; RV32IFD-NEXT: .LBB9_10: # %start
; RV32IFD-NEXT: bnez a2, .LBB11_4
; RV32IFD-NEXT: .LBB11_10: # %start
; RV32IFD-NEXT: mv a0, zero
; RV32IFD-NEXT: lui a5, 524288
; RV32IFD-NEXT: bnez a3, .LBB9_5
; RV32IFD-NEXT: .LBB9_11: # %start
; RV32IFD-NEXT: bnez a3, .LBB11_5
; RV32IFD-NEXT: .LBB11_11: # %start
; RV32IFD-NEXT: lui a1, 524288
; RV32IFD-NEXT: beqz a4, .LBB9_6
; RV32IFD-NEXT: .LBB9_12:
; RV32IFD-NEXT: beqz a4, .LBB11_6
; RV32IFD-NEXT: .LBB11_12:
; RV32IFD-NEXT: addi a1, a5, -1
; RV32IFD-NEXT: beqz a2, .LBB9_7
; RV32IFD-NEXT: j .LBB9_8
; RV32IFD-NEXT: beqz a2, .LBB11_7
; RV32IFD-NEXT: j .LBB11_8
;
; RV64IFD-LABEL: fcvt_l_d_sat:
; RV64IFD: # %bb.0: # %start
; RV64IFD-NEXT: lui a1, %hi(.LCPI9_0)
; RV64IFD-NEXT: fld ft1, %lo(.LCPI9_0)(a1)
; RV64IFD-NEXT: lui a1, %hi(.LCPI11_0)
; RV64IFD-NEXT: fld ft1, %lo(.LCPI11_0)(a1)
; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: fle.d a0, ft1, ft0
; RV64IFD-NEXT: addi a1, zero, -1
; RV64IFD-NEXT: bnez a0, .LBB9_2
; RV64IFD-NEXT: bnez a0, .LBB11_2
; RV64IFD-NEXT: # %bb.1: # %start
; RV64IFD-NEXT: slli a0, a1, 63
; RV64IFD-NEXT: j .LBB9_3
; RV64IFD-NEXT: .LBB9_2:
; RV64IFD-NEXT: j .LBB11_3
; RV64IFD-NEXT: .LBB11_2:
; RV64IFD-NEXT: fcvt.l.d a0, ft0, rtz
; RV64IFD-NEXT: .LBB9_3: # %start
; RV64IFD-NEXT: lui a2, %hi(.LCPI9_1)
; RV64IFD-NEXT: fld ft1, %lo(.LCPI9_1)(a2)
; RV64IFD-NEXT: .LBB11_3: # %start
; RV64IFD-NEXT: lui a2, %hi(.LCPI11_1)
; RV64IFD-NEXT: fld ft1, %lo(.LCPI11_1)(a2)
; RV64IFD-NEXT: flt.d a2, ft1, ft0
; RV64IFD-NEXT: bnez a2, .LBB9_6
; RV64IFD-NEXT: bnez a2, .LBB11_6
; RV64IFD-NEXT: # %bb.4: # %start
; RV64IFD-NEXT: feq.d a1, ft0, ft0
; RV64IFD-NEXT: beqz a1, .LBB9_7
; RV64IFD-NEXT: .LBB9_5: # %start
; RV64IFD-NEXT: beqz a1, .LBB11_7
; RV64IFD-NEXT: .LBB11_5: # %start
; RV64IFD-NEXT: ret
; RV64IFD-NEXT: .LBB9_6:
; RV64IFD-NEXT: .LBB11_6:
; RV64IFD-NEXT: srli a0, a1, 1
; RV64IFD-NEXT: feq.d a1, ft0, ft0
; RV64IFD-NEXT: bnez a1, .LBB9_5
; RV64IFD-NEXT: .LBB9_7: # %start
; RV64IFD-NEXT: bnez a1, .LBB11_5
; RV64IFD-NEXT: .LBB11_7: # %start
; RV64IFD-NEXT: mv a0, zero
; RV64IFD-NEXT: ret
start:
Expand Down Expand Up @@ -355,55 +401,55 @@ define i64 @fcvt_lu_d_sat(double %a) nounwind {
; RV32IFD-NEXT: fcvt.d.w ft0, zero
; RV32IFD-NEXT: fle.d a4, ft0, ft1
; RV32IFD-NEXT: mv a3, a0
; RV32IFD-NEXT: bnez a4, .LBB11_2
; RV32IFD-NEXT: bnez a4, .LBB13_2
; RV32IFD-NEXT: # %bb.1: # %start
; RV32IFD-NEXT: mv a3, zero
; RV32IFD-NEXT: .LBB11_2: # %start
; RV32IFD-NEXT: lui a0, %hi(.LCPI11_0)
; RV32IFD-NEXT: fld ft0, %lo(.LCPI11_0)(a0)
; RV32IFD-NEXT: .LBB13_2: # %start
; RV32IFD-NEXT: lui a0, %hi(.LCPI13_0)
; RV32IFD-NEXT: fld ft0, %lo(.LCPI13_0)(a0)
; RV32IFD-NEXT: flt.d a5, ft0, ft1
; RV32IFD-NEXT: addi a2, zero, -1
; RV32IFD-NEXT: addi a0, zero, -1
; RV32IFD-NEXT: beqz a5, .LBB11_7
; RV32IFD-NEXT: beqz a5, .LBB13_7
; RV32IFD-NEXT: # %bb.3: # %start
; RV32IFD-NEXT: beqz a4, .LBB11_8
; RV32IFD-NEXT: .LBB11_4: # %start
; RV32IFD-NEXT: bnez a5, .LBB11_6
; RV32IFD-NEXT: .LBB11_5: # %start
; RV32IFD-NEXT: beqz a4, .LBB13_8
; RV32IFD-NEXT: .LBB13_4: # %start
; RV32IFD-NEXT: bnez a5, .LBB13_6
; RV32IFD-NEXT: .LBB13_5: # %start
; RV32IFD-NEXT: mv a2, a1
; RV32IFD-NEXT: .LBB11_6: # %start
; RV32IFD-NEXT: .LBB13_6: # %start
; RV32IFD-NEXT: mv a1, a2
; RV32IFD-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 32
; RV32IFD-NEXT: ret
; RV32IFD-NEXT: .LBB11_7: # %start
; RV32IFD-NEXT: .LBB13_7: # %start
; RV32IFD-NEXT: mv a0, a3
; RV32IFD-NEXT: bnez a4, .LBB11_4
; RV32IFD-NEXT: .LBB11_8: # %start
; RV32IFD-NEXT: bnez a4, .LBB13_4
; RV32IFD-NEXT: .LBB13_8: # %start
; RV32IFD-NEXT: mv a1, zero
; RV32IFD-NEXT: beqz a5, .LBB11_5
; RV32IFD-NEXT: j .LBB11_6
; RV32IFD-NEXT: beqz a5, .LBB13_5
; RV32IFD-NEXT: j .LBB13_6
;
; RV64IFD-LABEL: fcvt_lu_d_sat:
; RV64IFD: # %bb.0: # %start
; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: fmv.d.x ft1, zero
; RV64IFD-NEXT: fle.d a0, ft1, ft0
; RV64IFD-NEXT: bnez a0, .LBB11_2
; RV64IFD-NEXT: bnez a0, .LBB13_2
; RV64IFD-NEXT: # %bb.1: # %start
; RV64IFD-NEXT: mv a1, zero
; RV64IFD-NEXT: j .LBB11_3
; RV64IFD-NEXT: .LBB11_2:
; RV64IFD-NEXT: j .LBB13_3
; RV64IFD-NEXT: .LBB13_2:
; RV64IFD-NEXT: fcvt.lu.d a1, ft0, rtz
; RV64IFD-NEXT: .LBB11_3: # %start
; RV64IFD-NEXT: lui a0, %hi(.LCPI11_0)
; RV64IFD-NEXT: fld ft1, %lo(.LCPI11_0)(a0)
; RV64IFD-NEXT: .LBB13_3: # %start
; RV64IFD-NEXT: lui a0, %hi(.LCPI13_0)
; RV64IFD-NEXT: fld ft1, %lo(.LCPI13_0)(a0)
; RV64IFD-NEXT: flt.d a2, ft1, ft0
; RV64IFD-NEXT: addi a0, zero, -1
; RV64IFD-NEXT: bnez a2, .LBB11_5
; RV64IFD-NEXT: bnez a2, .LBB13_5
; RV64IFD-NEXT: # %bb.4: # %start
; RV64IFD-NEXT: mv a0, a1
; RV64IFD-NEXT: .LBB11_5: # %start
; RV64IFD-NEXT: .LBB13_5: # %start
; RV64IFD-NEXT: ret
start:
%0 = tail call i64 @llvm.fptoui.sat.i64.f64(double %a)
Expand Down

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