[RISCV][InsertVSETVLI] Reorder code to reduce a future diff [nfc]

llvm · Dec 12, 2022 · b385c01 · b385c01
1 parent 78503e1
commit b385c01
Showing 1 changed file with 3 additions and 3 deletions.
diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -771,12 +771,12 @@ bool RISCVInsertVSETVLI::needVSETVLI(const MachineInstr &MI,
                                      const VSETVLIInfo &CurInfo) const {
   assert(Require == computeInfoForInstr(MI, MI.getDesc().TSFlags, MRI));
 
-  if (CurInfo.isCompatible(MI, Require))
-    return false;
-
   if (!CurInfo.isValid() || CurInfo.isUnknown() || CurInfo.hasSEWLMULRatioOnly())
     return true;
 
+  if (CurInfo.isCompatible(MI, Require))
+    return false;
+
   // For vmv.s.x and vfmv.s.f, there is only two behaviors, VL = 0 and VL > 0.
   // Additionally, if writing to an implicit_def operand, we don't need to
   // preserve any other bits and are thus compatible with any larger etype,