[RISCV] Mark zvkn* and zvks* extensions as enabled when all their sub…

…extensions are. These extensions don't contain any instructions on their own, they are just aliases for a set of extensions. We should set the preprocessor define anytime all the sub-extensions are supported. Reviewed By: kito-cheng, eopXD Differential Revision: https://reviews.llvm.org/D154171
llvm · Jun 30, 2023 · b4609b4 · b4609b4
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diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c
@@ -719,3 +719,55 @@
 // RUN: -march=rv64ifzvfbfwma0p6 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZVFBFWMA-EXT %s
 // CHECK-ZVFBFWMA-EXT: __riscv_zvfbfwma 6000{{$}}
+
+// RUN: %clang -target riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32iv_zvbb1p0_zvkned1p0_zvknhb1p0_zvkt1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-COMBINE-INTO-ZVKN %s
+// RUN: %clang -target riscv64 -menable-experimental-extensions \
+// RUN: -march=rv64iv_zvbb1p0_zvkned1p0_zvknhb1p0_zvkt1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-COMBINE-INTO-ZVKN %s
+// CHECK-COMBINE-INTO-ZVKN: __riscv_zvkn 1000000{{$}}
+
+// RUN: %clang -target riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32iv_zvbb1p0_zvbc1p0_zvkned1p0_zvknhb1p0_zvkt1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-COMBINE-INTO-ZVKNC %s
+// RUN: %clang -target riscv64 -menable-experimental-extensions \
+// RUN: -march=rv64iv_zvbb1p0_zvbc1p0_zvkned1p0_zvknhb1p0_zvkt1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-COMBINE-INTO-ZVKNC %s
+// CHECK-COMBINE-INTO-ZVKNC: __riscv_zvkn 1000000{{$}}
+// CHECK-COMBINE-INTO-ZVKNC: __riscv_zvknc 1000000{{$}}
+
+// RUN: %clang -target riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32iv_zvbb1p0_zvkg1p0_zvkned1p0_zvknhb1p0_zvkt1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-COMBINE-INTO-ZVKNG %s
+// RUN: %clang -target riscv64 -menable-experimental-extensions \
+// RUN: -march=rv64iv_zvbb1p0_zvkg1p0_zvkned1p0_zvknhb1p0_zvkt1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-COMBINE-INTO-ZVKNG %s
+// CHECK-COMBINE-INTO-ZVKNG: __riscv_zvkn 1000000{{$}}
+// CHECK-COMBINE-INTO-ZVKNG: __riscv_zvkng 1000000{{$}}
+
+// RUN: %clang -target riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32iv_zvbb1p0_zvksed1p0_zvksh1p0_zvkt1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-COMBINE-INTO-ZVKS %s
+// RUN: %clang -target riscv64 -menable-experimental-extensions \
+// RUN: -march=rv64iv_zvbb1p0_zvksed1p0_zvksh1p0_zvkt1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-COMBINE-INTO-ZVKS %s
+// CHECK-COMBINE-INTO-ZVKS: __riscv_zvks 1000000{{$}}
+
+// RUN: %clang -target riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32iv_zvbb1p0_zvbc1p0_zvksed1p0_zvksh1p0_zvkt1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-COMBINE-INTO-ZVKSC %s
+// RUN: %clang -target riscv64 -menable-experimental-extensions \
+// RUN: -march=rv64iv_zvbb1p0_zvbc1p0_zvksed1p0_zvksh1p0_zvkt1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-COMBINE-INTO-ZVKSC %s
+// CHECK-COMBINE-INTO-ZVKSC: __riscv_zvks 1000000{{$}}
+// CHECK-COMBINE-INTO-ZVKSC: __riscv_zvksc 1000000{{$}}
+
+// RUN: %clang -target riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32iv_zvbb1p0_zvkg1p0_zvksed1p0_zvksh1p0_zvkt1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-COMBINE-INTO-ZVKSG %s
+// RUN: %clang -target riscv64 -menable-experimental-extensions \
+// RUN: -march=rv64iv_zvbb1p0_zvkg1p0_zvksed1p0_zvksh1p0_zvkt1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-COMBINE-INTO-ZVKSG %s
+// CHECK-COMBINE-INTO-ZVKSG: __riscv_zvks 1000000{{$}}
+// CHECK-COMBINE-INTO-ZVKSG: __riscv_zvksg 1000000{{$}}
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -1095,6 +1095,12 @@ static constexpr CombinedExtsEntry CombineIntoExts[] = {
     {{"zk"}, {ImpliedExtsZk}},
     {{"zkn"}, {ImpliedExtsZkn}},
     {{"zks"}, {ImpliedExtsZks}},
+    {{"zvkn"}, {ImpliedExtsZvkn}},
+    {{"zvknc"}, {ImpliedExtsZvknc}},
+    {{"zvkng"}, {ImpliedExtsZvkng}},
+    {{"zvks"}, {ImpliedExtsZvks}},
+    {{"zvksc"}, {ImpliedExtsZvksc}},
+    {{"zvksg"}, {ImpliedExtsZvksg}},
 };
 
 void RISCVISAInfo::updateCombination() {