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Revert HWASAN failure (#74163)
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This is the failure:
https://lab.llvm.org/buildbot/#/builders/236/builds/7728/steps/10/logs/stdio

This started with eef8e1d, but because
there were a couple of patches that came after that I had to revert all
3 of them because of merge conflicts.
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@kstoimenov
kstoimenov committed Dec 2, 2023
1 parent 28eead0 commit b6d0ee0
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Showing 19 changed files with 7 additions and 336 deletions.
5 changes: 0 additions & 5 deletions clang/test/Driver/aarch64-v95a.c
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Expand Up @@ -13,8 +13,3 @@
// RUN: %clang -target aarch64_be -mbig-endian -march=armv9.5-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV95A-BE %s
// GENERICV95A-BE: "-cc1"{{.*}} "-triple" "aarch64_be{{.*}}" "-target-cpu" "generic" "-target-feature" "+neon" "-target-feature" "+v9.5a"

// ===== Features supported on aarch64 =====

// RUN: %clang -target aarch64 -march=armv9.5a+cpa -### -c %s 2>&1 | FileCheck -check-prefix=V95A-CPA %s
// RUN: %clang -target aarch64 -march=armv9.5-a+cpa -### -c %s 2>&1 | FileCheck -check-prefix=V95A-CPA %s
// V95A-CPA: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+neon" "-target-feature" "+v9.5a" "-target-feature" "+cpa"
5 changes: 1 addition & 4 deletions llvm/include/llvm/TargetParser/AArch64TargetParser.h
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Expand Up @@ -173,7 +173,6 @@ enum ArchExtKind : unsigned {
AEK_SMEF8F16 = 69, // FEAT_SME_F8F16
AEK_SMEF8F32 = 70, // FEAT_SME_F8F32
AEK_SMEFA64 = 71, // FEAT_SME_FA64
AEK_CPA = 72, // FEAT_CPA
AEK_NUM_EXTENSIONS
};
using ExtensionBitset = Bitset<AEK_NUM_EXTENSIONS>;
Expand Down Expand Up @@ -296,7 +295,6 @@ inline constexpr ExtensionInfo Extensions[] = {
{"sme-f8f16", AArch64::AEK_SMEF8F16, "+sme-f8f16", "-sme-f8f16", FEAT_INIT, "+sme2,+fp8", 0},
{"sme-f8f32", AArch64::AEK_SMEF8F32, "+sme-f8f32", "-sme-f8f32", FEAT_INIT, "+sme2,+fp8", 0},
{"sme-fa64", AArch64::AEK_SMEFA64, "+sme-fa64", "-sme-fa64", FEAT_INIT, "", 0},
{"cpa", AArch64::AEK_CPA, "+cpa", "-cpa", FEAT_INIT, "", 0},
// Special cases
{"none", AArch64::AEK_NONE, {}, {}, FEAT_INIT, "", ExtensionInfo::MaxFMVPriority},
};
Expand Down Expand Up @@ -380,8 +378,7 @@ inline constexpr ArchInfo ARMV9_3A = { VersionTuple{9, 3}, AProfile, "armv9.3-a
AArch64::ExtensionBitset({AArch64::AEK_MOPS, AArch64::AEK_HBC}))};
inline constexpr ArchInfo ARMV9_4A = { VersionTuple{9, 4}, AProfile, "armv9.4-a", "+v9.4a", (ARMV9_3A.DefaultExts |
AArch64::ExtensionBitset({AArch64::AEK_SPECRES2, AArch64::AEK_CSSC, AArch64::AEK_RASv2}))};
inline constexpr ArchInfo ARMV9_5A = { VersionTuple{9, 5}, AProfile, "armv9.5-a", "+v9.5a", (ARMV9_4A.DefaultExts |
AArch64::ExtensionBitset({AArch64::AEK_CPA}))};
inline constexpr ArchInfo ARMV9_5A = { VersionTuple{9, 5}, AProfile, "armv9.5-a", "+v9.5a", (ARMV9_4A.DefaultExts)};
// For v8-R, we do not enable crypto and align with GCC that enables a more minimal set of optional architecture extensions.
inline constexpr ArchInfo ARMV8R = { VersionTuple{8, 0}, RProfile, "armv8-r", "+v8r", (ARMV8_5A.DefaultExts |
AArch64::ExtensionBitset({AArch64::AEK_SSBS,
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5 changes: 1 addition & 4 deletions llvm/lib/Target/AArch64/AArch64.td
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Expand Up @@ -622,9 +622,6 @@ def FeatureLdpAlignedOnly : SubtargetFeature<"ldp-aligned-only", "HasLdpAlignedO
def FeatureStpAlignedOnly : SubtargetFeature<"stp-aligned-only", "HasStpAlignedOnly",
"true", "In order to emit stp, first check if the store will be aligned to 2 * element_size">;

def FeatureCPA : SubtargetFeature<"cpa", "HasCPA", "true",
"Enable ARMv9.5-A Checked Pointer Arithmetic (FEAT_CPA)">;

//===----------------------------------------------------------------------===//
// Architectures.
//
Expand Down Expand Up @@ -695,7 +692,7 @@ def HasV9_4aOps : SubtargetFeature<

def HasV9_5aOps : SubtargetFeature<
"v9.5a", "HasV9_5aOps", "true", "Support ARM v9.5a instructions",
[HasV9_4aOps, FeatureCPA]>;
[HasV9_4aOps]>;

def HasV8_0rOps : SubtargetFeature<
"v8r", "HasV8_0rOps", "true", "Support ARM v8r instructions",
Expand Down
52 changes: 0 additions & 52 deletions llvm/lib/Target/AArch64/AArch64InstrFormats.td
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Expand Up @@ -12446,58 +12446,6 @@ class SystemPXtI<bit L, string asm> :
BaseSYSPEncoding<L, asm, "\t$op1, $Cn, $Cm, $op2, $Rt", (outs),
(ins imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2, XSeqPairClassOperand:$Rt)>;

//----------------------------------------------------------------------------
// 2023 Armv9.5 Extensions
//----------------------------------------------------------------------------

//---
// Checked Pointer Arithmetic (FEAT_CPA)
//---

def LSLImm3ShiftOperand : AsmOperandClass {
let SuperClasses = [ExtendOperandLSL64];
let Name = "LSLImm3Shift";
let RenderMethod = "addLSLImm3ShifterOperands";
let DiagnosticType = "AddSubLSLImm3ShiftLarge";
}

def lsl_imm3_shift_operand : Operand<i32> {
let PrintMethod = "printShifter";
let ParserMatchClass = LSLImm3ShiftOperand;
}

// Base CPA scalar add/subtract with lsl #imm3 shift
class BaseAddSubCPA<bit isSub, string asm> : I<(outs GPR64sp:$Rd),
(ins GPR64sp:$Rn, GPR64:$Rm, lsl_imm3_shift_operand:$shift_imm),
asm, "\t$Rd, $Rn, $Rm$shift_imm", "", []>, Sched<[]> {
bits<5> Rd;
bits<5> Rn;
bits<5> Rm;
bits<3> shift_imm;
let Inst{31} = 0b1;
let Inst{30} = isSub;
let Inst{29-21} = 0b011010000;
let Inst{20-16} = Rm;
let Inst{15-13} = 0b001;
let Inst{12-10} = shift_imm;
let Inst{9-5} = Rn;
let Inst{4-0} = Rd;
}

// Alias for CPA scalar add/subtract with no shift
class AddSubCPAAlias<string asm, Instruction inst>
: InstAlias<asm#"\t$Rd, $Rn, $Rm",
(inst GPR64sp:$Rd, GPR64sp:$Rn, GPR64:$Rm, 0)>;

multiclass AddSubCPA<bit isSub, string asm> {
def _shift : BaseAddSubCPA<isSub, asm>;
def _noshift : AddSubCPAAlias<asm, !cast<Instruction>(NAME#"_shift")>;
}

class MulAccumCPA<bit isSub, string asm>
: BaseMulAccum<isSub, 0b011, GPR64, GPR64, asm, []>, Sched<[]> {
let Inst{31} = 0b1;
}

//----------------------------------------------------------------------------
// Allow the size specifier tokens to be upper case, not just lower.
Expand Down
19 changes: 0 additions & 19 deletions llvm/lib/Target/AArch64/AArch64InstrInfo.td
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Expand Up @@ -289,8 +289,6 @@ def HasCHK : Predicate<"Subtarget->hasCHK()">,
AssemblerPredicateWithAll<(all_of FeatureCHK), "chk">;
def HasGCS : Predicate<"Subtarget->hasGCS()">,
AssemblerPredicateWithAll<(all_of FeatureGCS), "gcs">;
def HasCPA : Predicate<"Subtarget->hasCPA()">,
AssemblerPredicateWithAll<(all_of FeatureCPA), "cpa">;
def IsLE : Predicate<"Subtarget->isLittleEndian()">;
def IsBE : Predicate<"!Subtarget->isLittleEndian()">;
def IsWindows : Predicate<"Subtarget->isTargetWindows()">;
Expand Down Expand Up @@ -9390,10 +9388,6 @@ let Predicates = [HasD128] in {
}
}

//===----------------------------===//
// 2023 Architecture Extensions:
//===----------------------------===//

let Predicates = [HasFP8] in {
defm F1CVTL : SIMDMixedTwoVectorFP8<0b00, "f1cvtl">;
defm F2CVTL : SIMDMixedTwoVectorFP8<0b01, "f2cvtl">;
Expand Down Expand Up @@ -9435,19 +9429,6 @@ let Predicates = [HasFP8DOT4] in {
defm FDOT : SIMDThreeSameVectorDOT4<"fdot">;
} // End let Predicates = [HasFP8DOT4]

//===----------------------------------------------------------------------===//
// Checked Pointer Arithmetic (FEAT_CPA)
//===----------------------------------------------------------------------===//
let Predicates = [HasCPA] in {
// Scalar add/subtract
defm ADDPT : AddSubCPA<0, "addpt">;
defm SUBPT : AddSubCPA<1, "subpt">;

// Scalar multiply-add/subtract
def MADDPT : MulAccumCPA<0, "maddpt">;
def MSUBPT : MulAccumCPA<1, "msubpt">;
}

include "AArch64InstrAtomics.td"
include "AArch64SVEInstrInfo.td"
include "AArch64SMEInstrInfo.td"
Expand Down
21 changes: 0 additions & 21 deletions llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
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Expand Up @@ -4163,24 +4163,3 @@ let Predicates = [HasSVE2orSME2, HasLUT] in {
// LUTI4 (two contiguous registers)
defm LUTI4_Z2ZZI : sve2_luti4_vector_vg2_index<"luti4">;
} // End HasSVE2orSME2, HasLUT

//===----------------------------------------------------------------------===//
// Checked Pointer Arithmetic (FEAT_CPA)
//===----------------------------------------------------------------------===//
let Predicates = [HasSVE, HasCPA] in {
// Add/subtract (vectors, unpredicated)
def ADD_ZZZ_CPA : sve_int_bin_cons_arit_0<0b11, 0b010, "addpt", ZPR64>;
def SUB_ZZZ_CPA : sve_int_bin_cons_arit_0<0b11, 0b011, "subpt", ZPR64>;

// Add/subtract (vectors, predicated)
let DestructiveInstType = DestructiveBinaryComm in {
def ADD_ZPmZ_CPA : sve_int_bin_pred_arit_log<0b11, 0b00, 0b100, "addpt", ZPR64>;
def SUB_ZPmZ_CPA : sve_int_bin_pred_arit_log<0b11, 0b00, 0b101, "subpt", ZPR64>;
}

// Multiply-add vectors, writing multiplicand
def MAD_CPA : sve_int_mad_cpa<"madpt">;

// Multiply-add vectors, writing addend
def MLA_CPA : sve_int_mla_cpa<"mlapt">;
}
2 changes: 1 addition & 1 deletion llvm/lib/Target/AArch64/AArch64SchedA64FX.td
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Expand Up @@ -24,7 +24,7 @@ def A64FXModel : SchedMachineModel {
[HasSVE2, HasSVE2AES, HasSVE2SM4, HasSVE2SHA3, HasSVE2BitPerm, HasPAuth,
HasSVE2orSME, HasMTE, HasMatMulInt8, HasBF16, HasSME2, HasSME2p1, HasSVE2p1,
HasSVE2p1_or_HasSME2p1, HasSMEF16F16, HasSSVE_FP8FMA, HasSMEF8F16, HasSMEF8F32,
HasSMEFA64, HasCPA];
HasSMEFA64];

let FullInstRWOverlapCheck = 0;
}
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td
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Expand Up @@ -19,7 +19,7 @@ def NeoverseN2Model : SchedMachineModel {
let CompleteModel = 1;

list<Predicate> UnsupportedFeatures = !listconcat(SMEUnsupported.F,
[HasSVE2p1, HasCPA]);
[HasSVE2p1]);
}

//===----------------------------------------------------------------------===//
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td
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Expand Up @@ -28,7 +28,7 @@ def NeoverseV1Model : SchedMachineModel {

list<Predicate> UnsupportedFeatures = !listconcat(SVE2Unsupported.F,
SMEUnsupported.F,
[HasMTE, HasCPA]);
[HasMTE]);
}

//===----------------------------------------------------------------------===//
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
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Expand Up @@ -22,7 +22,7 @@ def NeoverseV2Model : SchedMachineModel {
let CompleteModel = 1;

list<Predicate> UnsupportedFeatures = !listconcat(SMEUnsupported.F,
[HasSVE2p1, HasCPA]);
[HasSVE2p1]);
}

//===----------------------------------------------------------------------===//
Expand Down
18 changes: 0 additions & 18 deletions llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
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Expand Up @@ -1541,13 +1541,6 @@ class AArch64Operand : public MCParsedAsmOperand {
getShiftExtendAmount() <= 4;
}

bool isLSLImm3Shift() const {
if (!isShiftExtend())
return false;
AArch64_AM::ShiftExtendType ET = getShiftExtendType();
return ET == AArch64_AM::LSL && getShiftExtendAmount() <= 7;
}

template<int Width> bool isMemXExtend() const {
if (!isExtend())
return false;
Expand Down Expand Up @@ -2098,12 +2091,6 @@ class AArch64Operand : public MCParsedAsmOperand {
Inst.addOperand(MCOperand::createImm(Imm));
}

void addLSLImm3ShifterOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
unsigned Imm = getShiftExtendAmount();
Inst.addOperand(MCOperand::createImm(Imm));
}

void addSyspXzrPairOperand(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");

Expand Down Expand Up @@ -3677,7 +3664,6 @@ static const struct Extension {
{"sme-f8f16", {AArch64::FeatureSMEF8F16}},
{"sme-f8f32", {AArch64::FeatureSMEF8F32}},
{"sme-fa64", {AArch64::FeatureSMEFA64}},
{"cpa", {AArch64::FeatureCPA}},
};

static void setRequiredFeatureString(FeatureBitset FBS, std::string &Str) {
Expand Down Expand Up @@ -6078,9 +6064,6 @@ bool AArch64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode,
"Invalid vector list, expected list with each SVE vector in the list "
"4 registers apart, and the first register in the range [z0, z3] or "
"[z16, z19] and with correct element type");
case Match_AddSubLSLImm3ShiftLarge:
return Error(Loc,
"expected 'lsl' with optional integer in range [0, 7]");
default:
llvm_unreachable("unexpected error code!");
}
Expand Down Expand Up @@ -6465,7 +6448,6 @@ bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
case Match_InvalidMemoryIndexed8:
case Match_InvalidMemoryIndexed16:
case Match_InvalidCondCode:
case Match_AddSubLSLImm3ShiftLarge:
case Match_AddSubRegExtendSmall:
case Match_AddSubRegExtendLarge:
case Match_AddSubSecondSource:
Expand Down
31 changes: 0 additions & 31 deletions llvm/lib/Target/AArch64/SVEInstrFormats.td
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Original file line number Diff line number Diff line change
Expand Up @@ -10424,34 +10424,3 @@ multiclass sve2_luti4_vector_vg2_index<string mnemonic> {
let Inst{23-22} = idx;
}
}

//===----------------------------------------------------------------------===//
// Checked Pointer Arithmetic (FEAT_CPA)
//===----------------------------------------------------------------------===//
class sve_int_mad_cpa<string asm>
: I<(outs ZPR64:$Zdn), (ins ZPR64:$_Zdn, ZPR64:$Zm, ZPR64:$Za),
asm, "\t$Zdn, $Zm, $Za", "", []>, Sched<[]> {
bits<5> Zdn;
bits<5> Zm;
bits<5> Za;
let Inst{31-24} = 0b01000100;
let Inst{23-22} = 0b11; // sz
let Inst{21} = 0b0;
let Inst{20-16} = Zm;
let Inst{15} = 0b1;
let Inst{14-10} = 0b10110; // opc
let Inst{9-5} = Za;
let Inst{4-0} = Zdn;

let Constraints = "$Zdn = $_Zdn";
let DestructiveInstType = DestructiveOther;
let ElementSize = ZPR64.ElementSize;
let hasSideEffects = 0;
}

class sve_int_mla_cpa<string asm>
: sve2_int_mla<0b11, 0b10100, asm, ZPR64, ZPR64> {
let Inst{15} = 0b1;

let ElementSize = ZPR64.ElementSize;
}
69 changes: 0 additions & 69 deletions llvm/test/MC/AArch64/SVE/armv9.5a-cpa.s
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