[RISCV] Add DAG combine to fold (sub 0, (setcc x, 0, setlt)) -> (sra …

…x , xlen - 1)

The result of sub + setcc is 0 or 1 for all bits.
The sra instruction get the same result.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D147538

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

@@ -9130,10 +9130,23 @@ static SDValue performSUBCombine(SDNode *N, SelectionDAG &DAG,
   if (SDValue V = combineSubOfBoolean(N, DAG))
     return V;
 
-  // fold (sub x, (select lhs, rhs, cc, 0, y)) ->
-  //      (select lhs, rhs, cc, x, (sub x, y))
   SDValue N0 = N->getOperand(0);
   SDValue N1 = N->getOperand(1);
+  // fold (sub 0, (setcc x, 0, setlt)) -> (sra x, xlen - 1)
+  if (isNullConstant(N0) && N1.getOpcode() == ISD::SETCC && N1.hasOneUse() &&
+      isNullConstant(N1.getOperand(1))) {
+    ISD::CondCode CCVal = cast<CondCodeSDNode>(N1.getOperand(2))->get();
+    if (CCVal == ISD::SETLT) {
+      EVT VT = N->getValueType(0);
+      SDLoc DL(N);
+      unsigned ShAmt = N0.getValueSizeInBits() - 1;
+      return DAG.getNode(ISD::SRA, DL, VT, N1.getOperand(0),
+                         DAG.getConstant(ShAmt, DL, VT));
+    }
+  }
+
+  // fold (sub x, (select lhs, rhs, cc, 0, y)) ->
+  //      (select lhs, rhs, cc, x, (sub x, y))
   return combineSelectAndUse(N, N1, N0, DAG, /*AllOnes*/ false, Subtarget);
 }
 

llvm/test/CodeGen/RISCV/alu64.ll

@@ -219,8 +219,7 @@ define i64 @sll(i64 %a, i64 %b) nounwind {
 ; RV32I-NEXT:    srl a0, a0, a2
 ; RV32I-NEXT:    or a1, a1, a0
 ; RV32I-NEXT:  .LBB11_3:
-; RV32I-NEXT:    slti a0, a4, 0
-; RV32I-NEXT:    neg a0, a0
+; RV32I-NEXT:    srai a0, a4, 31
 ; RV32I-NEXT:    and a0, a0, a3
 ; RV32I-NEXT:    ret
   %1 = shl i64 %a, %b
@@ -307,8 +306,7 @@ define i64 @srl(i64 %a, i64 %b) nounwind {
 ; RV32I-NEXT:    sll a1, a1, a2
 ; RV32I-NEXT:    or a0, a0, a1
 ; RV32I-NEXT:  .LBB15_3:
-; RV32I-NEXT:    slti a1, a4, 0
-; RV32I-NEXT:    neg a1, a1
+; RV32I-NEXT:    srai a1, a4, 31
 ; RV32I-NEXT:    and a1, a1, a3
 ; RV32I-NEXT:    ret
   %1 = lshr i64 %a, %b

llvm/test/CodeGen/RISCV/bittest.ll

@@ -367,7 +367,7 @@ define i1 @bittest_constant_by_var_shr_i64(i64 %b) nounwind {
 ; RV32-NEXT:    addi a1, a1, 722
 ; RV32-NEXT:    srl a1, a1, a0
 ; RV32-NEXT:    addi a0, a0, -32
-; RV32-NEXT:    slti a0, a0, 0
+; RV32-NEXT:    srli a0, a0, 31
 ; RV32-NEXT:    and a0, a0, a1
 ; RV32-NEXT:    ret
 ;
@@ -407,7 +407,7 @@ define i1 @bittest_constant_by_var_shl_i64(i64 %b) nounwind {
 ; RV32-NEXT:    addi a1, a1, 722
 ; RV32-NEXT:    srl a1, a1, a0
 ; RV32-NEXT:    addi a0, a0, -32
-; RV32-NEXT:    slti a0, a0, 0
+; RV32-NEXT:    srli a0, a0, 31
 ; RV32-NEXT:    and a0, a0, a1
 ; RV32-NEXT:    ret
 ;

llvm/test/CodeGen/RISCV/fpclamptosat.ll

@@ -1969,8 +1969,7 @@ define i32 @stest_f64i32_mm(double %x) {
 ; RV32IF-NEXT:  .LBB27_3: # %entry
 ; RV32IF-NEXT:    mv a0, a3
 ; RV32IF-NEXT:  .LBB27_4: # %entry
-; RV32IF-NEXT:    slti a3, a1, 0
-; RV32IF-NEXT:    neg a3, a3
+; RV32IF-NEXT:    srai a3, a1, 31
 ; RV32IF-NEXT:    and a1, a3, a1
 ; RV32IF-NEXT:    mv a3, a0
 ; RV32IF-NEXT:    bltz a1, .LBB27_11
@@ -2302,8 +2301,7 @@ define i32 @stest_f16i32_mm(half %x) {
 ; RV32-NEXT:  .LBB33_3: # %entry
 ; RV32-NEXT:    mv a0, a3
 ; RV32-NEXT:  .LBB33_4: # %entry
-; RV32-NEXT:    slti a3, a1, 0
-; RV32-NEXT:    neg a3, a3
+; RV32-NEXT:    srai a3, a1, 31
 ; RV32-NEXT:    and a1, a3, a1
 ; RV32-NEXT:    mv a3, a0
 ; RV32-NEXT:    bltz a1, .LBB33_11
@@ -3072,8 +3070,7 @@ define i64 @stest_f64i64_mm(double %x) {
 ; RV64IF-NEXT:  .LBB45_3: # %entry
 ; RV64IF-NEXT:    mv a0, a3
 ; RV64IF-NEXT:  .LBB45_4: # %entry
-; RV64IF-NEXT:    slti a3, a1, 0
-; RV64IF-NEXT:    neg a3, a3
+; RV64IF-NEXT:    srai a3, a1, 63
 ; RV64IF-NEXT:    and a1, a3, a1
 ; RV64IF-NEXT:    slli a4, a2, 63
 ; RV64IF-NEXT:    mv a3, a0
@@ -3845,8 +3842,7 @@ define i64 @stest_f16i64_mm(half %x) {
 ; RV64-NEXT:  .LBB51_3: # %entry
 ; RV64-NEXT:    mv a0, a3
 ; RV64-NEXT:  .LBB51_4: # %entry
-; RV64-NEXT:    slti a3, a1, 0
-; RV64-NEXT:    neg a3, a3
+; RV64-NEXT:    srai a3, a1, 63
 ; RV64-NEXT:    and a1, a3, a1
 ; RV64-NEXT:    slli a4, a2, 63
 ; RV64-NEXT:    mv a3, a0