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[VE] Support intrinsic to isnert/extract_subreg of v512i1
Support insert/extract_subreg intrinsic instructions for v512i1 registers and add regression tests. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D94298
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; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s | ||
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;;; Test extract intrinsic instructions | ||
;;; | ||
;;; Note: | ||
;;; We test extract_vm512u and extract_vm512l pseudo instructions. | ||
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; Function Attrs: nounwind readnone | ||
define fastcc <256 x i1> @extract_vm512u(<512 x i1> %0) { | ||
; CHECK-LABEL: extract_vm512u: | ||
; CHECK: # %bb.0: | ||
; CHECK-NEXT: andm %vm1, %vm0, %vm2 | ||
; CHECK-NEXT: b.l.t (, %s10) | ||
%2 = tail call <256 x i1> @llvm.ve.vl.extract.vm512u(<512 x i1> %0) | ||
ret <256 x i1> %2 | ||
} | ||
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; Function Attrs: nounwind readnone | ||
declare <256 x i1> @llvm.ve.vl.extract.vm512u(<512 x i1>) | ||
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; Function Attrs: nounwind readnone | ||
define fastcc <256 x i1> @extract_vm512l(<512 x i1> %0) { | ||
; CHECK-LABEL: extract_vm512l: | ||
; CHECK: # %bb.0: | ||
; CHECK-NEXT: andm %vm0, %vm0, %vm2 | ||
; CHECK-NEXT: andm %vm1, %vm0, %vm3 | ||
; CHECK-NEXT: b.l.t (, %s10) | ||
%2 = tail call <256 x i1> @llvm.ve.vl.extract.vm512l(<512 x i1> %0) | ||
ret <256 x i1> %2 | ||
} | ||
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; Function Attrs: nounwind readnone | ||
declare <256 x i1> @llvm.ve.vl.extract.vm512l(<512 x i1>) |
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,32 @@ | ||
; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s | ||
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;;; Test insert intrinsic instructions | ||
;;; | ||
;;; Note: | ||
;;; We test insert_vm512u and insert_vm512l pseudo instructions. | ||
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; Function Attrs: nounwind readnone | ||
define fastcc <512 x i1> @insert_vm512u(<512 x i1> %0, <256 x i1> %1) { | ||
; CHECK-LABEL: insert_vm512u: | ||
; CHECK: # %bb.0: | ||
; CHECK-NEXT: andm %vm2, %vm0, %vm4 | ||
; CHECK-NEXT: b.l.t (, %s10) | ||
%3 = tail call <512 x i1> @llvm.ve.vl.insert.vm512u(<512 x i1> %0, <256 x i1> %1) | ||
ret <512 x i1> %3 | ||
} | ||
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; Function Attrs: nounwind readnone | ||
declare <512 x i1> @llvm.ve.vl.insert.vm512u(<512 x i1>, <256 x i1>) | ||
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; Function Attrs: nounwind readnone | ||
define fastcc <512 x i1> @insert_vm512l(<512 x i1> %0, <256 x i1> %1) { | ||
; CHECK-LABEL: insert_vm512l: | ||
; CHECK: # %bb.0: | ||
; CHECK-NEXT: andm %vm3, %vm0, %vm4 | ||
; CHECK-NEXT: b.l.t (, %s10) | ||
%3 = tail call <512 x i1> @llvm.ve.vl.insert.vm512l(<512 x i1> %0, <256 x i1> %1) | ||
ret <512 x i1> %3 | ||
} | ||
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; Function Attrs: nounwind readnone | ||
declare <512 x i1> @llvm.ve.vl.insert.vm512l(<512 x i1>, <256 x i1>) |