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[X86] Add SchedWrites for CMOV and SETCC. Use them to remove InstRWs.
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Summary:
Cmov and setcc previously used WriteALU, but on Intel processors at least they are more restricted than basic ALU ops.

This patch adds new SchedWrites for them and removes the InstRWs. I had to leave some InstRWs for CMOVA/CMOVBE and SETA/SETBE because those have an extra uop relative to the other condition codes on Intel CPUs.

The test changes are due to fixing a missing ZnAGU dependency on the memory form of setcc.

Reviewers: RKSimon, andreadb, GGanesh

Reviewed By: RKSimon

Subscribers: GGanesh, llvm-commits

Differential Revision: https://reviews.llvm.org/D45380

llvm-svn: 329539
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@topperc
topperc committed Apr 8, 2018
1 parent c362f42 commit b7baa35
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Showing 11 changed files with 79 additions and 92 deletions.
8 changes: 4 additions & 4 deletions llvm/lib/Target/X86/X86InstrCMovSetCC.td
View file
Expand Up @@ -16,7 +16,7 @@
// CMOV instructions.
multiclass CMOV<bits<8> opc, string Mnemonic, PatLeaf CondNode> {
let Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst",
isCommutable = 1, SchedRW = [WriteALU] in {
isCommutable = 1, SchedRW = [WriteCMOV] in {
def NAME#16rr
: I<opc, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
!strconcat(Mnemonic, "{w}\t{$src2, $dst|$dst, $src2}"),
Expand All @@ -38,7 +38,7 @@ multiclass CMOV<bits<8> opc, string Mnemonic, PatLeaf CondNode> {
}

let Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst",
SchedRW = [WriteALULd, ReadAfterLd] in {
SchedRW = [WriteCMOVLd, ReadAfterLd] in {
def NAME#16rm
: I<opc, MRMSrcMem, (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
!strconcat(Mnemonic, "{w}\t{$src2, $dst|$dst, $src2}"),
Expand Down Expand Up @@ -85,11 +85,11 @@ multiclass SETCC<bits<8> opc, string Mnemonic, PatLeaf OpNode> {
def r : I<opc, MRMXr, (outs GR8:$dst), (ins),
!strconcat(Mnemonic, "\t$dst"),
[(set GR8:$dst, (X86setcc OpNode, EFLAGS))],
IIC_SET_R>, TB, Sched<[WriteALU]>;
IIC_SET_R>, TB, Sched<[WriteSETCC]>;
def m : I<opc, MRMXm, (outs), (ins i8mem:$dst),
!strconcat(Mnemonic, "\t$dst"),
[(store (X86setcc OpNode, EFLAGS), addr:$dst)],
IIC_SET_M>, TB, Sched<[WriteALU, WriteStore]>;
IIC_SET_M>, TB, Sched<[WriteSETCCStore]>;
} // Uses = [EFLAGS]
}

Expand Down
17 changes: 7 additions & 10 deletions llvm/lib/Target/X86/X86SchedBroadwell.td
View file
Expand Up @@ -113,6 +113,13 @@ def : WriteRes<WriteIMulH, []> { let Latency = 3; } // Integer multiplication, h

def : WriteRes<WriteLEA, [BWPort15]>; // LEA instructions can't fold loads.

defm : BWWriteResPair<WriteCMOV, [BWPort06], 1>; // Conditional move.
def : WriteRes<WriteSETCC, [BWPort06]>; // Setcc.
def : WriteRes<WriteSETCCStore, [BWPort06,BWPort4,BWPort237]> {
let Latency = 2;
let NumMicroOps = 3;
}

// Bit counts.
defm : BWWriteResPair<WriteBitScan, [BWPort1], 3>;
defm : BWWriteResPair<WriteLZCNT, [BWPort1], 3>;
Expand Down Expand Up @@ -469,7 +476,6 @@ def: InstRW<[BWWriteResGroup6], (instregex "ADC(16|32|64)ri",
"BTR(16|32|64)rr",
"BTS(16|32|64)ri8",
"BTS(16|32|64)rr",
"CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rr",
"J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_1",
"J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_4",
"JMP_1",
Expand All @@ -481,7 +487,6 @@ def: InstRW<[BWWriteResGroup6], (instregex "ADC(16|32|64)ri",
"SBB(16|32|64)ri",
"SBB(16|32|64)i",
"SBB(8|16|32|64)rr",
"SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)r",
"SHL(8|16|32|64)r1",
"SHL(8|16|32|64)ri",
"SHLX(32|64)rr",
Expand Down Expand Up @@ -791,13 +796,6 @@ def BWWriteResGroup22 : SchedWriteRes<[BWPort4,BWPort6,BWPort237]> {
}
def: InstRW<[BWWriteResGroup22], (instregex "FNSTCW16m")>;

def BWWriteResGroup23 : SchedWriteRes<[BWPort4,BWPort237,BWPort06]> {
let Latency = 2;
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
def: InstRW<[BWWriteResGroup23], (instregex "SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)m")>;

def BWWriteResGroup24 : SchedWriteRes<[BWPort4,BWPort237,BWPort15]> {
let Latency = 2;
let NumMicroOps = 3;
Expand Down Expand Up @@ -1398,7 +1396,6 @@ def BWWriteResGroup63 : SchedWriteRes<[BWPort23,BWPort06]> {
let ResourceCycles = [1,1];
}
def: InstRW<[BWWriteResGroup63], (instregex "BT(16|32|64)mi8",
"CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rm",
"RORX(32|64)mi",
"SARX(32|64)rm",
"SHLX(32|64)rm",
Expand Down
17 changes: 7 additions & 10 deletions llvm/lib/Target/X86/X86SchedHaswell.td
View file
Expand Up @@ -119,6 +119,13 @@ defm : HWWriteResPair<WriteShift, [HWPort06], 1>;
defm : HWWriteResPair<WriteJump, [HWPort06], 1>;
defm : HWWriteResPair<WriteCRC32, [HWPort1], 3>;

defm : HWWriteResPair<WriteCMOV, [HWPort06,HWPort0156], 2, [1,1], 2>; // Conditional move.
def : WriteRes<WriteSETCC, [HWPort06]>; // Setcc.
def : WriteRes<WriteSETCCStore, [HWPort06,HWPort4,HWPort237]> {
let Latency = 2;
let NumMicroOps = 3;
}

// This is for simple LEAs with one or two input operands.
// The complex ones can only execute on port 1, and they require two cycles on
// the port to read all inputs. We don't model that.
Expand Down Expand Up @@ -830,7 +837,6 @@ def: InstRW<[HWWriteResGroup7], (instregex "BT(16|32|64)ri8",
"SAR(8|16|32|64)r1",
"SAR(8|16|32|64)ri",
"SARX(32|64)rr",
"SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)r",
"SHL(8|16|32|64)r1",
"SHL(8|16|32|64)ri",
"SHLX(32|64)rr",
Expand Down Expand Up @@ -1405,13 +1411,6 @@ def HWWriteResGroup21 : SchedWriteRes<[HWPort4,HWPort6,HWPort237]> {
}
def: InstRW<[HWWriteResGroup21], (instregex "FNSTCW16m")>;

def HWWriteResGroup22 : SchedWriteRes<[HWPort4,HWPort237,HWPort06]> {
let Latency = 2;
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
def: InstRW<[HWWriteResGroup22], (instregex "SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)m")>;

def HWWriteResGroup23 : SchedWriteRes<[HWPort4,HWPort237,HWPort15]> {
let Latency = 2;
let NumMicroOps = 3;
Expand Down Expand Up @@ -1568,7 +1567,6 @@ def: InstRW<[HWWriteResGroup35], (instrs CWD, JCXZ, JECXZ, JRCXZ)>;
def: InstRW<[HWWriteResGroup35], (instregex "ADC(8|16|32|64)ri",
"ADC(8|16|32|64)rr",
"ADC(8|16|32|64)i",
"CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rr",
"SBB(8|16|32|64)ri",
"SBB(8|16|32|64)rr",
"SBB(8|16|32|64)i",
Expand Down Expand Up @@ -1663,7 +1661,6 @@ def HWWriteResGroup43 : SchedWriteRes<[HWPort23,HWPort06,HWPort0156]> {
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
def: InstRW<[HWWriteResGroup43], (instregex "CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rm")>;
def: InstRW<[HWWriteResGroup43, ReadAfterLd], (instrs ADC8rm, ADC16rm, ADC32rm, ADC64rm,
SBB8rm, SBB16rm, SBB32rm, SBB64rm)>;

Expand Down
17 changes: 7 additions & 10 deletions llvm/lib/Target/X86/X86SchedSandyBridge.td
View file
Expand Up @@ -110,6 +110,13 @@ defm : SBWriteResPair<WriteShift, [SBPort05], 1>;
defm : SBWriteResPair<WriteJump, [SBPort5], 1>;
defm : SBWriteResPair<WriteCRC32, [SBPort1], 3, [1], 1, 5>;

defm : SBWriteResPair<WriteCMOV, [SBPort05,SBPort015], 2, [1,1], 2>; // Conditional move.
def : WriteRes<WriteSETCC, [SBPort05]>; // Setcc.
def : WriteRes<WriteSETCCStore, [SBPort05,SBPort4,SBPort23]> {
let Latency = 2;
let NumMicroOps = 3;
}

// This is for simple LEAs with one or two input operands.
// The complex ones can only execute on port 1, and they require two cycles on
// the port to read all inputs. We don't model that.
Expand Down Expand Up @@ -382,7 +389,6 @@ def: InstRW<[SBWriteResGroup4], (instregex "BT(16|32|64)ri8",
"SAHF",
"SAR(8|16|32|64)ri",
"SAR(8|16|32|64)r1",
"SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)r",
"SHL(8|16|32|64)ri",
"SHL(8|16|32|64)r1",
"SHR(8|16|32|64)ri",
Expand Down Expand Up @@ -624,7 +630,6 @@ def SBWriteResGroup19 : SchedWriteRes<[SBPort05,SBPort015]> {
def: InstRW<[SBWriteResGroup19], (instregex "ADC(8|16|32|64)ri",
"ADC(8|16|32|64)rr",
"ADC(8|16|32|64)i",
"CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rr",
"SBB(8|16|32|64)ri",
"SBB(8|16|32|64)rr",
"SBB(8|16|32|64)i",
Expand Down Expand Up @@ -949,13 +954,6 @@ def SBWriteResGroup37 : SchedWriteRes<[SBPort4,SBPort01,SBPort23]> {
def: InstRW<[SBWriteResGroup37], (instregex "VMASKMOVPD(Y?)mr",
"VMASKMOVPS(Y?)mr")>;

def SBWriteResGroup38 : SchedWriteRes<[SBPort4,SBPort23,SBPort05]> {
let Latency = 2;
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
def: InstRW<[SBWriteResGroup38], (instregex "SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)m")>;

def SBWriteResGroup39 : SchedWriteRes<[SBPort4,SBPort23,SBPort15]> {
let Latency = 5;
let NumMicroOps = 3;
Expand Down Expand Up @@ -1297,7 +1295,6 @@ def SBWriteResGroup65 : SchedWriteRes<[SBPort23,SBPort05,SBPort015]> {
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
def: InstRW<[SBWriteResGroup65], (instregex "CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rm")>;
def: InstRW<[SBWriteResGroup65, ReadAfterLd], (instrs ADC8rm, ADC16rm, ADC32rm, ADC64rm,
SBB8rm, SBB16rm, SBB32rm, SBB64rm)>;

Expand Down
17 changes: 7 additions & 10 deletions llvm/lib/Target/X86/X86SchedSkylakeClient.td
View file
Expand Up @@ -113,6 +113,13 @@ defm : SKLWriteResPair<WriteCRC32, [SKLPort1], 3>;
def : WriteRes<WriteIMulH, []> { let Latency = 3; } // Integer multiplication, high part.
def : WriteRes<WriteLEA, [SKLPort15]>; // LEA instructions can't fold loads.

defm : SKLWriteResPair<WriteCMOV, [SKLPort06], 1>; // Conditional move.
def : WriteRes<WriteSETCC, [SKLPort06]>; // Setcc.
def : WriteRes<WriteSETCCStore, [SKLPort06,SKLPort4,SKLPort237]> {
let Latency = 2;
let NumMicroOps = 3;
}

// Bit counts.
defm : SKLWriteResPair<WriteBitScan, [SKLPort1], 3>;
defm : SKLWriteResPair<WriteLZCNT, [SKLPort1], 3>;
Expand Down Expand Up @@ -534,7 +541,6 @@ def: InstRW<[SKLWriteResGroup7], (instregex "ADC(16|32|64)ri",
"BTS(16|32|64)ri8",
"BTS(16|32|64)rr",
"CLAC",
"CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rr",
"J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_1",
"J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_4",
"JMP_1",
Expand All @@ -546,7 +552,6 @@ def: InstRW<[SKLWriteResGroup7], (instregex "ADC(16|32|64)ri",
"SBB(16|32|64)ri",
"SBB(16|32|64)i",
"SBB(8|16|32|64)rr",
"SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)r",
"SHL(8|16|32|64)r1",
"SHL(8|16|32|64)ri",
"SHLX(32|64)rr",
Expand Down Expand Up @@ -812,13 +817,6 @@ def SKLWriteResGroup25 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort237]> {
}
def: InstRW<[SKLWriteResGroup25], (instregex "FNSTCW16m")>;

def SKLWriteResGroup26 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort06]> {
let Latency = 2;
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
def: InstRW<[SKLWriteResGroup26], (instregex "SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)m")>;

def SKLWriteResGroup27 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort15]> {
let Latency = 2;
let NumMicroOps = 3;
Expand Down Expand Up @@ -1421,7 +1419,6 @@ def SKLWriteResGroup74 : SchedWriteRes<[SKLPort23,SKLPort06]> {
let ResourceCycles = [1,1];
}
def: InstRW<[SKLWriteResGroup74], (instregex "BT(16|32|64)mi8",
"CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rm",
"RORX(32|64)mi",
"SARX(32|64)rm",
"SHLX(32|64)rm",
Expand Down
17 changes: 7 additions & 10 deletions llvm/lib/Target/X86/X86SchedSkylakeServer.td
View file
Expand Up @@ -113,6 +113,13 @@ defm : SKXWriteResPair<WriteCRC32, [SKXPort1], 3>;
def : WriteRes<WriteIMulH, []> { let Latency = 3; } // Integer multiplication, high part.
def : WriteRes<WriteLEA, [SKXPort15]>; // LEA instructions can't fold loads.

defm : SKXWriteResPair<WriteCMOV, [SKXPort06], 1>; // Conditional move.
def : WriteRes<WriteSETCC, [SKXPort06]>; // Setcc.
def : WriteRes<WriteSETCCStore, [SKXPort06,SKXPort4,SKXPort237]> {
let Latency = 2;
let NumMicroOps = 3;
}

// Integer shifts and rotates.
defm : SKXWriteResPair<WriteShift, [SKXPort06], 1>;

Expand Down Expand Up @@ -1010,7 +1017,6 @@ def: InstRW<[SKXWriteResGroup7], (instregex "ADC(16|32|64)ri",
"BTS(16|32|64)ri8",
"BTS(16|32|64)rr",
"CLAC",
"CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rr",
"J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_1",
"J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_4",
"JMP_1",
Expand All @@ -1022,7 +1028,6 @@ def: InstRW<[SKXWriteResGroup7], (instregex "ADC(16|32|64)ri",
"SBB(16|32|64)ri",
"SBB(16|32|64)i",
"SBB(8|16|32|64)rr",
"SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)r",
"SHL(8|16|32|64)r1",
"SHL(8|16|32|64)ri",
"SHLX(32|64)rr",
Expand Down Expand Up @@ -1617,13 +1622,6 @@ def SKXWriteResGroup25 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort237]> {
}
def: InstRW<[SKXWriteResGroup25], (instregex "FNSTCW16m")>;

def SKXWriteResGroup26 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort06]> {
let Latency = 2;
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
def: InstRW<[SKXWriteResGroup26], (instregex "SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)m")>;

def SKXWriteResGroup27 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort15]> {
let Latency = 2;
let NumMicroOps = 3;
Expand Down Expand Up @@ -3050,7 +3048,6 @@ def SKXWriteResGroup78 : SchedWriteRes<[SKXPort23,SKXPort06]> {
let ResourceCycles = [1,1];
}
def: InstRW<[SKXWriteResGroup78], (instregex "BT(16|32|64)mi8",
"CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rm",
"RORX(32|64)mi",
"SARX(32|64)rm",
"SHLX(32|64)rm",
Expand Down
15 changes: 9 additions & 6 deletions llvm/lib/Target/X86/X86Schedule.td
View file
Expand Up @@ -39,9 +39,14 @@ multiclass X86SchedWritePair {
}
}

// Loads, stores, and moves, not folded with other operations.
def WriteLoad : SchedWrite;
def WriteStore : SchedWrite;
def WriteMove : SchedWrite;

// Arithmetic.
defm WriteALU : X86SchedWritePair; // Simple integer ALU op.
def WriteALURMW : WriteSequence<[WriteALULd, WriteRMW]>;
def WriteALURMW : WriteSequence<[WriteALULd, WriteStore]>;
defm WriteIMul : X86SchedWritePair; // Integer multiplication.
def WriteIMulH : SchedWrite; // Integer multiplication, high part.
defm WriteIDiv : X86SchedWritePair; // Integer division.
Expand All @@ -51,6 +56,9 @@ defm WriteBitScan : X86SchedWritePair; // Bit scan forward/reverse.
defm WritePOPCNT : X86SchedWritePair; // Bit population count.
defm WriteLZCNT : X86SchedWritePair; // Leading zero count.
defm WriteTZCNT : X86SchedWritePair; // Trailing zero count.
defm WriteCMOV : X86SchedWritePair; // Conditional move.
def WriteSETCC : SchedWrite; // Set register based on condition code.
def WriteSETCCStore : SchedWrite;

// Integer shifts and rotates.
defm WriteShift : X86SchedWritePair;
Expand All @@ -59,11 +67,6 @@ defm WriteShift : X86SchedWritePair;
defm WriteBEXTR : X86SchedWritePair;
defm WriteBZHI : X86SchedWritePair;

// Loads, stores, and moves, not folded with other operations.
def WriteLoad : SchedWrite;
def WriteStore : SchedWrite;
def WriteMove : SchedWrite;

// Idioms that clear a register, like xorps %xmm0, %xmm0.
// These can often bypass execution ports completely.
def WriteZero : SchedWrite;
Expand Down
4 changes: 4 additions & 0 deletions llvm/lib/Target/X86/X86ScheduleBtVer2.td
View file
Expand Up @@ -141,6 +141,10 @@ defm : JWriteResIntPair<WriteIMul, [JALU1, JMul], 3, [1, 1], 2>; // i8/i16/i32
defm : JWriteResIntPair<WriteIDiv, [JALU1, JDiv], 41, [1, 41], 2>; // Worst case (i64 division)
defm : JWriteResIntPair<WriteCRC32, [JALU01], 3, [4], 3>;

defm : JWriteResIntPair<WriteCMOV, [JALU01], 1>; // Conditional move.
def : WriteRes<WriteSETCC, [JALU01]>; // Setcc.
def : WriteRes<WriteSETCCStore, [JALU01,JSAGU]>;

def : WriteRes<WriteIMulH, [JALU1]> {
let Latency = 6;
let ResourceCycles = [4];
Expand Down
7 changes: 7 additions & 0 deletions llvm/lib/Target/X86/X86ScheduleSLM.td
View file
Expand Up @@ -93,6 +93,13 @@ defm : SLMWriteResPair<WriteShift, [SLM_IEC_RSV0], 1>;
defm : SLMWriteResPair<WriteJump, [SLM_IEC_RSV1], 1>;
defm : SLMWriteResPair<WriteCRC32, [SLM_IEC_RSV1], 3>;

defm : SLMWriteResPair<WriteCMOV, [SLM_IEC_RSV01], 1>;
def : WriteRes<WriteSETCC, [SLM_IEC_RSV01]>;
def : WriteRes<WriteSETCCStore, [SLM_IEC_RSV01, SLM_MEC_RSV]> {
// FIXME Latency and NumMicrOps?
let ResourceCycles = [2,1];
}

// This is for simple LEAs with one or two input operands.
// The complex ones can only execute on port 1, and they require two cycles on
// the port to read all inputs. We don't model that.
Expand Down
20 changes: 4 additions & 16 deletions llvm/lib/Target/X86/X86ScheduleZnver1.td
View file
Expand Up @@ -153,6 +153,10 @@ defm : ZnWriteResPair<WriteShift, [ZnALU], 1>;
defm : ZnWriteResPair<WriteJump, [ZnALU], 1>;
defm : ZnWriteResFpuPair<WriteCRC32, [ZnFPU0], 3>;

defm : ZnWriteResPair<WriteCMOV, [ZnALU], 1>;
def : WriteRes<WriteSETCC, [ZnALU]>;
def : WriteRes<WriteSETCCStore, [ZnALU, ZnAGU]>;

// Bit counts.
defm : ZnWriteResPair<WriteBitScan, [ZnALU], 3>;
defm : ZnWriteResPair<WriteLZCNT, [ZnALU], 2>;
Expand Down Expand Up @@ -277,14 +281,6 @@ def : InstRW<[WriteALULd, ReadAfterLd], (instregex "MOV16rm")>;
// r,m.
def : InstRW<[WriteLoad], (instregex "MOV(S|Z)X32rm(8|16)")>;

// CMOVcc.
// r,r.
def : InstRW<[WriteALU],
(instregex "CMOV(O|NO|B|AE|E|NE|BE|A|S|NS|P|NP|L|GE|LE|G)(16|32|64)rr")>;
// r,m.
def : InstRW<[WriteALULd, ReadAfterLd],
(instregex "CMOV(O|NO|B|AE|E|NE|BE|A|S|NS|P|NP|L|GE|LE|G)(16|32|64)rm")>;

// XCHG.
// r,r.
def ZnWriteXCHG : SchedWriteRes<[ZnALU]> {
Expand Down Expand Up @@ -614,14 +610,6 @@ def : InstRW<[WriteMicrocoded], (instregex "SHRD(16|32|64)rrCL")>;
// m,r,cl.
def : InstRW<[WriteMicrocoded], (instregex "SH(R|L)D(16|32|64)mrCL")>;

// SETcc.
// r.
def : InstRW<[WriteShift],
(instregex "SET(O|NO|B|AE|E|NE|BE|A|S|NS|P|NP|L|GE|LE|G)r")>;
// m.
def : InstRW<[WriteShift],
(instregex "SET(O|NO|B|AE|E|NE|BE|A|S|NS|P|NP|L|GE|LE|G)m")>;

//-- Misc instructions --//
// CMPXCHG.
def ZnWriteCMPXCHG : SchedWriteRes<[ZnAGU, ZnALU]> {
Expand Down

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