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[ARM] Tidy-up condition-code support functions
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Move condition code support functions to Utils and remove code duplication.

Reviewed by: @fhahn, @asb
Differential Revision: https://reviews.llvm.org/D37179

llvm-svn: 311860
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@javedabsar
javedabsar committed Aug 27, 2017
1 parent 7298595 commit b81fa99
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Showing 3 changed files with 89 additions and 102 deletions.
40 changes: 2 additions & 38 deletions llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
View file
Expand Up @@ -3339,25 +3339,7 @@ ARMAsmParser::parseITCondCode(OperandVector &Operands) {
const AsmToken &Tok = Parser.getTok();
if (!Tok.is(AsmToken::Identifier))
return MatchOperand_NoMatch;
unsigned CC = StringSwitch<unsigned>(Tok.getString().lower())
.Case("eq", ARMCC::EQ)
.Case("ne", ARMCC::NE)
.Case("hs", ARMCC::HS)
.Case("cs", ARMCC::HS)
.Case("lo", ARMCC::LO)
.Case("cc", ARMCC::LO)
.Case("mi", ARMCC::MI)
.Case("pl", ARMCC::PL)
.Case("vs", ARMCC::VS)
.Case("vc", ARMCC::VC)
.Case("hi", ARMCC::HI)
.Case("ls", ARMCC::LS)
.Case("ge", ARMCC::GE)
.Case("lt", ARMCC::LT)
.Case("gt", ARMCC::GT)
.Case("le", ARMCC::LE)
.Case("al", ARMCC::AL)
.Default(~0U);
unsigned CC = ARMCondCodeFromString(Tok.getString());
if (CC == ~0U)
return MatchOperand_NoMatch;
Parser.Lex(); // Eat the token.
Expand Down Expand Up @@ -5340,25 +5322,7 @@ StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
Mnemonic != "sbcs" && Mnemonic != "rscs") {
unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
.Case("eq", ARMCC::EQ)
.Case("ne", ARMCC::NE)
.Case("hs", ARMCC::HS)
.Case("cs", ARMCC::HS)
.Case("lo", ARMCC::LO)
.Case("cc", ARMCC::LO)
.Case("mi", ARMCC::MI)
.Case("pl", ARMCC::PL)
.Case("vs", ARMCC::VS)
.Case("vc", ARMCC::VC)
.Case("hi", ARMCC::HI)
.Case("ls", ARMCC::LS)
.Case("ge", ARMCC::GE)
.Case("lt", ARMCC::LT)
.Case("gt", ARMCC::GT)
.Case("le", ARMCC::LE)
.Case("al", ARMCC::AL)
.Default(~0U);
unsigned CC = ARMCondCodeFromString(Mnemonic.substr(Mnemonic.size()-2));
if (CC != ~0U) {
Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
PredicationCode = CC;
Expand Down
65 changes: 1 addition & 64 deletions llvm/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h
View file
Expand Up @@ -19,73 +19,10 @@

#include "ARMMCTargetDesc.h"
#include "llvm/Support/ErrorHandling.h"
#include "Utils/ARMBaseInfo.h"

namespace llvm {

// Enums corresponding to ARM condition codes
namespace ARMCC {
// The CondCodes constants map directly to the 4-bit encoding of the
// condition field for predicated instructions.
enum CondCodes { // Meaning (integer) Meaning (floating-point)
EQ, // Equal Equal
NE, // Not equal Not equal, or unordered
HS, // Carry set >, ==, or unordered
LO, // Carry clear Less than
MI, // Minus, negative Less than
PL, // Plus, positive or zero >, ==, or unordered
VS, // Overflow Unordered
VC, // No overflow Not unordered
HI, // Unsigned higher Greater than, or unordered
LS, // Unsigned lower or same Less than or equal
GE, // Greater than or equal Greater than or equal
LT, // Less than Less than, or unordered
GT, // Greater than Greater than
LE, // Less than or equal <, ==, or unordered
AL // Always (unconditional) Always (unconditional)
};

inline static CondCodes getOppositeCondition(CondCodes CC) {
switch (CC) {
default: llvm_unreachable("Unknown condition code");
case EQ: return NE;
case NE: return EQ;
case HS: return LO;
case LO: return HS;
case MI: return PL;
case PL: return MI;
case VS: return VC;
case VC: return VS;
case HI: return LS;
case LS: return HI;
case GE: return LT;
case LT: return GE;
case GT: return LE;
case LE: return GT;
}
}
} // namespace ARMCC

inline static const char *ARMCondCodeToString(ARMCC::CondCodes CC) {
switch (CC) {
case ARMCC::EQ: return "eq";
case ARMCC::NE: return "ne";
case ARMCC::HS: return "hs";
case ARMCC::LO: return "lo";
case ARMCC::MI: return "mi";
case ARMCC::PL: return "pl";
case ARMCC::VS: return "vs";
case ARMCC::VC: return "vc";
case ARMCC::HI: return "hi";
case ARMCC::LS: return "ls";
case ARMCC::GE: return "ge";
case ARMCC::LT: return "lt";
case ARMCC::GT: return "gt";
case ARMCC::LE: return "le";
case ARMCC::AL: return "al";
}
llvm_unreachable("Unknown condition code");
}

namespace ARM_PROC {
enum IMod {
IE = 2,
Expand Down
86 changes: 86 additions & 0 deletions llvm/lib/Target/ARM/Utils/ARMBaseInfo.h
View file
Expand Up @@ -24,6 +24,92 @@

namespace llvm {

// Enums corresponding to ARM condition codes
namespace ARMCC {
// The CondCodes constants map directly to the 4-bit encoding of the
// condition field for predicated instructions.
enum CondCodes { // Meaning (integer) Meaning (floating-point)
EQ, // Equal Equal
NE, // Not equal Not equal, or unordered
HS, // Carry set >, ==, or unordered
LO, // Carry clear Less than
MI, // Minus, negative Less than
PL, // Plus, positive or zero >, ==, or unordered
VS, // Overflow Unordered
VC, // No overflow Not unordered
HI, // Unsigned higher Greater than, or unordered
LS, // Unsigned lower or same Less than or equal
GE, // Greater than or equal Greater than or equal
LT, // Less than Less than, or unordered
GT, // Greater than Greater than
LE, // Less than or equal <, ==, or unordered
AL // Always (unconditional) Always (unconditional)
};

inline static CondCodes getOppositeCondition(CondCodes CC) {
switch (CC) {
default: llvm_unreachable("Unknown condition code");
case EQ: return NE;
case NE: return EQ;
case HS: return LO;
case LO: return HS;
case MI: return PL;
case PL: return MI;
case VS: return VC;
case VC: return VS;
case HI: return LS;
case LS: return HI;
case GE: return LT;
case LT: return GE;
case GT: return LE;
case LE: return GT;
}
}
} // end namespace ARMCC

inline static const char *ARMCondCodeToString(ARMCC::CondCodes CC) {
switch (CC) {
case ARMCC::EQ: return "eq";
case ARMCC::NE: return "ne";
case ARMCC::HS: return "hs";
case ARMCC::LO: return "lo";
case ARMCC::MI: return "mi";
case ARMCC::PL: return "pl";
case ARMCC::VS: return "vs";
case ARMCC::VC: return "vc";
case ARMCC::HI: return "hi";
case ARMCC::LS: return "ls";
case ARMCC::GE: return "ge";
case ARMCC::LT: return "lt";
case ARMCC::GT: return "gt";
case ARMCC::LE: return "le";
case ARMCC::AL: return "al";
}
llvm_unreachable("Unknown condition code");
}

inline static unsigned ARMCondCodeFromString(StringRef CC) {
return StringSwitch<unsigned>(CC.lower())
.Case("eq", ARMCC::EQ)
.Case("ne", ARMCC::NE)
.Case("hs", ARMCC::HS)
.Case("cs", ARMCC::HS)
.Case("lo", ARMCC::LO)
.Case("cc", ARMCC::LO)
.Case("mi", ARMCC::MI)
.Case("pl", ARMCC::PL)
.Case("vs", ARMCC::VS)
.Case("vc", ARMCC::VC)
.Case("hi", ARMCC::HI)
.Case("ls", ARMCC::LS)
.Case("ge", ARMCC::GE)
.Case("lt", ARMCC::LT)
.Case("gt", ARMCC::GT)
.Case("le", ARMCC::LE)
.Case("al", ARMCC::AL)
.Default(~0U);
}

// System Registers
namespace ARMSysReg {
struct MClassSysReg {
Expand Down

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