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[InstCombine] Simplify icmp ult/uge (shl %x, C2), C1 iff C1 is power …
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…of two -> icmp eq/ne (and %x, (lshr -C1, C2)), 0.

Simplify 'shl' inequality test into 'and' equality test.

This pattern happens in the middle-end while simplifying bitfield access,
Exposed in https://reviews.llvm.org/D63505

https://rise4fun.com/Alive/6uz

Reviewers: lebedev.ri, efriedma

Reviewed By: lebedev.ri

Subscribers: spatel, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D63675

llvm-svn: 364348
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@huihzhang
huihzhang committed Jun 25, 2019
1 parent dcd7eb7 commit b90cb57
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Showing 3 changed files with 47 additions and 26 deletions.
21 changes: 21 additions & 0 deletions llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
View file
Expand Up @@ -2028,6 +2028,27 @@ Instruction *InstCombiner::foldICmpShlConstant(ICmpInst &Cmp,
And, Constant::getNullValue(ShType));
}

// Simplify 'shl' inequality test into 'and' equality test.
if (Cmp.isUnsigned() && Shl->hasOneUse()) {
// (X l<< C2) u<=/u> C1 iff C1+1 is power of two -> X & (~C1 l>> C2) ==/!= 0
if ((C + 1).isPowerOf2() &&
(Pred == ICmpInst::ICMP_ULE || Pred == ICmpInst::ICMP_UGT)) {
Value *And = Builder.CreateAnd(X, (~C).lshr(ShiftAmt->getZExtValue()));
return new ICmpInst(Pred == ICmpInst::ICMP_ULE ? ICmpInst::ICMP_EQ
: ICmpInst::ICMP_NE,
And, Constant::getNullValue(ShType));
}
// (X l<< C2) u</u>= C1 iff C1 is power of two -> X & (-C1 l>> C2) ==/!= 0
if (C.isPowerOf2() &&
(Pred == ICmpInst::ICMP_ULT || Pred == ICmpInst::ICMP_UGE)) {
Value *And =
Builder.CreateAnd(X, (~(C - 1)).lshr(ShiftAmt->getZExtValue()));
return new ICmpInst(Pred == ICmpInst::ICMP_ULT ? ICmpInst::ICMP_EQ
: ICmpInst::ICMP_NE,
And, Constant::getNullValue(ShType));
}
}

// Transform (icmp pred iM (shl iM %v, N), C)
// -> (icmp pred i(M-N) (trunc %v iM to i(M-N)), (trunc (C>>N))
// Transform the shl to a trunc if (trunc (C>>N)) has no loss and M-N.
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/Transforms/InstCombine/pr17827.ll
View file
Expand Up @@ -66,8 +66,8 @@ define <2 x i1> @test_shift_and_cmp_changed1_vec(<2 x i8> %p, <2 x i8> %q) {
; Unsigned compare allows a transformation to compare against 0.
define i1 @test_shift_and_cmp_changed2(i8 %p) {
; CHECK-LABEL: @test_shift_and_cmp_changed2(
; CHECK-NEXT: [[SHLP:%.*]] = shl i8 [[P:%.*]], 5
; CHECK-NEXT: [[CMP:%.*]] = icmp ult i8 [[SHLP]], 64
; CHECK-NEXT: [[TMP1:%.*]] = and i8 [[P:%.*]], 6
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[TMP1]], 0
; CHECK-NEXT: ret i1 [[CMP]]
;
%shlp = shl i8 %p, 5
Expand All @@ -78,8 +78,8 @@ define i1 @test_shift_and_cmp_changed2(i8 %p) {

define <2 x i1> @test_shift_and_cmp_changed2_vec(<2 x i8> %p) {
; CHECK-LABEL: @test_shift_and_cmp_changed2_vec(
; CHECK-NEXT: [[SHLP:%.*]] = shl <2 x i8> [[P:%.*]], <i8 5, i8 5>
; CHECK-NEXT: [[CMP:%.*]] = icmp ult <2 x i8> [[SHLP]], <i8 64, i8 64>
; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i8> [[P:%.*]], <i8 6, i8 6>
; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i8> [[TMP1]], zeroinitializer
; CHECK-NEXT: ret <2 x i1> [[CMP]]
;
%shlp = shl <2 x i8> %p, <i8 5, i8 5>
Expand Down
44 changes: 22 additions & 22 deletions llvm/test/Transforms/InstCombine/shl-unsigned-cmp-const.ll
View file
Expand Up @@ -9,8 +9,8 @@
; C2 Shift amount smaller than C1 trailing zeros.
define i1 @scalar_i8_shl_ult_const_1(i8 %x) {
; CHECK-LABEL: @scalar_i8_shl_ult_const_1(
; CHECK-NEXT: [[SHL:%.*]] = shl i8 [[X:%.*]], 5
; CHECK-NEXT: [[CMP:%.*]] = icmp ult i8 [[SHL]], 64
; CHECK-NEXT: [[TMP1:%.*]] = and i8 [[X:%.*]], 6
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[TMP1]], 0
; CHECK-NEXT: ret i1 [[CMP]]
;
%shl = shl i8 %x, 5
Expand Down Expand Up @@ -45,8 +45,8 @@ define i1 @scalar_i8_shl_ult_const_3(i8 %x) {
; C2 Shift amount smaller than C1 trailing zeros.
define i1 @scalar_i16_shl_ult_const(i16 %x) {
; CHECK-LABEL: @scalar_i16_shl_ult_const(
; CHECK-NEXT: [[SHL:%.*]] = shl i16 [[X:%.*]], 8
; CHECK-NEXT: [[CMP:%.*]] = icmp ult i16 [[SHL]], 1024
; CHECK-NEXT: [[TMP1:%.*]] = and i16 [[X:%.*]], 252
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i16 [[TMP1]], 0
; CHECK-NEXT: ret i1 [[CMP]]
;
%shl = shl i16 %x, 8
Expand All @@ -56,8 +56,8 @@ define i1 @scalar_i16_shl_ult_const(i16 %x) {

define i1 @scalar_i32_shl_ult_const(i32 %x) {
; CHECK-LABEL: @scalar_i32_shl_ult_const(
; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[X:%.*]], 11
; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[SHL]], 131072
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 2097088
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[TMP1]], 0
; CHECK-NEXT: ret i1 [[CMP]]
;
%shl = shl i32 %x, 11
Expand All @@ -67,8 +67,8 @@ define i1 @scalar_i32_shl_ult_const(i32 %x) {

define i1 @scalar_i64_shl_ult_const(i64 %x) {
; CHECK-LABEL: @scalar_i64_shl_ult_const(
; CHECK-NEXT: [[SHL:%.*]] = shl i64 [[X:%.*]], 25
; CHECK-NEXT: [[CMP:%.*]] = icmp ult i64 [[SHL]], 8589934592
; CHECK-NEXT: [[TMP1:%.*]] = and i64 [[X:%.*]], 549755813632
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[TMP1]], 0
; CHECK-NEXT: ret i1 [[CMP]]
;
%shl = shl i64 %x, 25
Expand All @@ -79,8 +79,8 @@ define i1 @scalar_i64_shl_ult_const(i64 %x) {
; Check 'uge' predicate
define i1 @scalar_i8_shl_uge_const(i8 %x) {
; CHECK-LABEL: @scalar_i8_shl_uge_const(
; CHECK-NEXT: [[SHL:%.*]] = shl i8 [[X:%.*]], 5
; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i8 [[SHL]], 63
; CHECK-NEXT: [[TMP1:%.*]] = and i8 [[X:%.*]], 6
; CHECK-NEXT: [[CMP:%.*]] = icmp ne i8 [[TMP1]], 0
; CHECK-NEXT: ret i1 [[CMP]]
;
%shl = shl i8 %x, 5
Expand All @@ -91,8 +91,8 @@ define i1 @scalar_i8_shl_uge_const(i8 %x) {
; Check 'ule' predicate
define i1 @scalar_i8_shl_ule_const(i8 %x) {
; CHECK-LABEL: @scalar_i8_shl_ule_const(
; CHECK-NEXT: [[SHL:%.*]] = shl i8 [[X:%.*]], 5
; CHECK-NEXT: [[CMP:%.*]] = icmp ult i8 [[SHL]], 64
; CHECK-NEXT: [[TMP1:%.*]] = and i8 [[X:%.*]], 6
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[TMP1]], 0
; CHECK-NEXT: ret i1 [[CMP]]
;
%shl = shl i8 %x, 5
Expand All @@ -103,8 +103,8 @@ define i1 @scalar_i8_shl_ule_const(i8 %x) {
; Check 'ugt' predicate
define i1 @scalar_i8_shl_ugt_const(i8 %x) {
; CHECK-LABEL: @scalar_i8_shl_ugt_const(
; CHECK-NEXT: [[SHL:%.*]] = shl i8 [[X:%.*]], 5
; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i8 [[SHL]], 63
; CHECK-NEXT: [[TMP1:%.*]] = and i8 [[X:%.*]], 6
; CHECK-NEXT: [[CMP:%.*]] = icmp ne i8 [[TMP1]], 0
; CHECK-NEXT: ret i1 [[CMP]]
;
%shl = shl i8 %x, 5
Expand All @@ -116,8 +116,8 @@ define i1 @scalar_i8_shl_ugt_const(i8 %x) {

define <4 x i1> @vector_4xi32_shl_ult_const(<4 x i32> %x) {
; CHECK-LABEL: @vector_4xi32_shl_ult_const(
; CHECK-NEXT: [[SHL:%.*]] = shl <4 x i32> [[X:%.*]], <i32 11, i32 11, i32 11, i32 11>
; CHECK-NEXT: [[CMP:%.*]] = icmp ult <4 x i32> [[SHL]], <i32 131072, i32 131072, i32 131072, i32 131072>
; CHECK-NEXT: [[TMP1:%.*]] = and <4 x i32> [[X:%.*]], <i32 2097088, i32 2097088, i32 2097088, i32 2097088>
; CHECK-NEXT: [[CMP:%.*]] = icmp eq <4 x i32> [[TMP1]], zeroinitializer
; CHECK-NEXT: ret <4 x i1> [[CMP]]
;
%shl = shl <4 x i32> %x, <i32 11, i32 11, i32 11, i32 11>
Expand Down Expand Up @@ -161,8 +161,8 @@ define <4 x i1> @vector_4xi32_shl_ult_const_undef3(<4 x i32> %x) {
; Check 'uge' predicate
define <4 x i1> @vector_4xi32_shl_uge_const(<4 x i32> %x) {
; CHECK-LABEL: @vector_4xi32_shl_uge_const(
; CHECK-NEXT: [[SHL:%.*]] = shl <4 x i32> [[X:%.*]], <i32 11, i32 11, i32 11, i32 11>
; CHECK-NEXT: [[CMP:%.*]] = icmp ugt <4 x i32> [[SHL]], <i32 131071, i32 131071, i32 131071, i32 131071>
; CHECK-NEXT: [[TMP1:%.*]] = and <4 x i32> [[X:%.*]], <i32 2097088, i32 2097088, i32 2097088, i32 2097088>
; CHECK-NEXT: [[CMP:%.*]] = icmp ne <4 x i32> [[TMP1]], zeroinitializer
; CHECK-NEXT: ret <4 x i1> [[CMP]]
;
%shl = shl <4 x i32> %x, <i32 11, i32 11, i32 11, i32 11>
Expand All @@ -173,8 +173,8 @@ define <4 x i1> @vector_4xi32_shl_uge_const(<4 x i32> %x) {
; Check 'ule' predicate
define <4 x i1> @vector_4xi32_shl_ule_const(<4 x i32> %x) {
; CHECK-LABEL: @vector_4xi32_shl_ule_const(
; CHECK-NEXT: [[SHL:%.*]] = shl <4 x i32> [[X:%.*]], <i32 11, i32 11, i32 11, i32 11>
; CHECK-NEXT: [[CMP:%.*]] = icmp ult <4 x i32> [[SHL]], <i32 131072, i32 131072, i32 131072, i32 131072>
; CHECK-NEXT: [[TMP1:%.*]] = and <4 x i32> [[X:%.*]], <i32 2097088, i32 2097088, i32 2097088, i32 2097088>
; CHECK-NEXT: [[CMP:%.*]] = icmp eq <4 x i32> [[TMP1]], zeroinitializer
; CHECK-NEXT: ret <4 x i1> [[CMP]]
;
%shl = shl <4 x i32> %x, <i32 11, i32 11, i32 11, i32 11>
Expand All @@ -185,8 +185,8 @@ define <4 x i1> @vector_4xi32_shl_ule_const(<4 x i32> %x) {
; Check 'ugt' predicate
define <4 x i1> @vector_4xi32_shl_ugt_const(<4 x i32> %x) {
; CHECK-LABEL: @vector_4xi32_shl_ugt_const(
; CHECK-NEXT: [[SHL:%.*]] = shl <4 x i32> [[X:%.*]], <i32 11, i32 11, i32 11, i32 11>
; CHECK-NEXT: [[CMP:%.*]] = icmp ugt <4 x i32> [[SHL]], <i32 131071, i32 131071, i32 131071, i32 131071>
; CHECK-NEXT: [[TMP1:%.*]] = and <4 x i32> [[X:%.*]], <i32 2097088, i32 2097088, i32 2097088, i32 2097088>
; CHECK-NEXT: [[CMP:%.*]] = icmp ne <4 x i32> [[TMP1]], zeroinitializer
; CHECK-NEXT: ret <4 x i1> [[CMP]]
;
%shl = shl <4 x i32> %x, <i32 11, i32 11, i32 11, i32 11>
Expand Down

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