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[M68k][NFC] Use Register instead of unsigned int
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@tclin914
tclin914 committed Jan 13, 2022
1 parent cc1b9ac commit bb13036
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Showing 3 changed files with 22 additions and 22 deletions.
16 changes: 8 additions & 8 deletions llvm/lib/Target/M68k/M68kFrameLowering.cpp
View file
Expand Up @@ -157,7 +157,7 @@ static unsigned findDeadCallerSavedReg(MachineBasicBlock &MBB,
MachineOperand &MO = MBBI->getOperand(i);
if (!MO.isReg() || MO.isDef())
continue;
unsigned Reg = MO.getReg();
Register Reg = MO.getReg();
if (!Reg)
continue;
for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
Expand Down Expand Up @@ -463,7 +463,7 @@ void M68kFrameLowering::emitPrologueCalleeSavedFrameMoves(
// Calculate offsets.
for (const auto &I : CSI) {
int64_t Offset = MFI.getObjectOffset(I.getFrameIdx());
unsigned Reg = I.getReg();
Register Reg = I.getReg();

unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
BuildCFI(MBB, MBBI, DL,
Expand All @@ -485,7 +485,7 @@ void M68kFrameLowering::emitPrologue(MachineFunction &MF,
uint64_t StackSize = MFI.getStackSize(); // Number of bytes to allocate.
bool HasFP = hasFP(MF);
bool NeedsDwarfCFI = MMI.hasDebugInfo() || Fn.needsUnwindTableEntry();
unsigned FramePtr = TRI->getFrameRegister(MF);
Register FramePtr = TRI->getFrameRegister(MF);
const unsigned MachineFramePtr = FramePtr;
unsigned BasePtr = TRI->getBaseRegister();

Expand Down Expand Up @@ -683,7 +683,7 @@ void M68kFrameLowering::emitEpilogue(MachineFunction &MF,
DebugLoc DL;
if (MBBI != MBB.end())
DL = MBBI->getDebugLoc();
unsigned FramePtr = TRI->getFrameRegister(MF);
Register FramePtr = TRI->getFrameRegister(MF);
unsigned MachineFramePtr = FramePtr;

// Get the number of bytes to allocate from the FrameInfo.
Expand Down Expand Up @@ -819,7 +819,7 @@ bool M68kFrameLowering::assignCalleeSavedSpillSlots(
// Since emitPrologue and emitEpilogue will handle spilling and restoring of
// the frame register, we can delete it from CSI list and not have to worry
// about avoiding it later.
unsigned FPReg = TRI->getFrameRegister(MF);
Register FPReg = TRI->getFrameRegister(MF);
for (unsigned i = 0, e = CSI.size(); i < e; ++i) {
if (TRI->regsOverlap(CSI[i].getReg(), FPReg)) {
CSI.erase(CSI.begin() + i);
Expand All @@ -842,7 +842,7 @@ bool M68kFrameLowering::spillCalleeSavedRegisters(
unsigned Mask = 0;
for (const auto &Info : CSI) {
FI = std::max(FI, Info.getFrameIdx());
unsigned Reg = Info.getReg();
Register Reg = Info.getReg();
unsigned Shift = MRI.getSpillRegisterOrder(Reg);
Mask |= 1 << Shift;
}
Expand All @@ -856,7 +856,7 @@ bool M68kFrameLowering::spillCalleeSavedRegisters(
const MachineFunction &MF = *MBB.getParent();
const MachineRegisterInfo &RI = MF.getRegInfo();
for (const auto &Info : CSI) {
unsigned Reg = Info.getReg();
Register Reg = Info.getReg();
bool IsLiveIn = RI.isLiveIn(Reg);
if (!IsLiveIn)
MBB.addLiveIn(Reg);
Expand All @@ -877,7 +877,7 @@ bool M68kFrameLowering::restoreCalleeSavedRegisters(
unsigned Mask = 0;
for (const auto &Info : CSI) {
FI = std::max(FI, Info.getFrameIdx());
unsigned Reg = Info.getReg();
Register Reg = Info.getReg();
unsigned Shift = MRI.getSpillRegisterOrder(Reg);
Mask |= 1 << Shift;
}
Expand Down
16 changes: 8 additions & 8 deletions llvm/lib/Target/M68k/M68kISelLowering.cpp
View file
Expand Up @@ -268,7 +268,7 @@ static bool MatchingStackOffset(SDValue Arg, unsigned Offset,

int FI = INT_MAX;
if (Arg.getOpcode() == ISD::CopyFromReg) {
unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
Register VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
if (!Register::isVirtualRegister(VR))
return false;
MachineInstr *Def = MRI->getVRegDef(VR);
Expand Down Expand Up @@ -900,7 +900,7 @@ SDValue M68kTargetLowering::LowerFormalArguments(
else
llvm_unreachable("Unknown argument type!");

unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
Register Reg = MF.addLiveIn(VA.getLocReg(), RC);
ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);

// If this is an 8 or 16-bit value, it is really passed promoted to 32
Expand Down Expand Up @@ -1276,7 +1276,7 @@ bool M68kTargetLowering::IsEligibleForTailCallOptimization(
CCValAssign &VA = ArgLocs[i];
if (!VA.isRegLoc())
continue;
unsigned Reg = VA.getLocReg();
Register Reg = VA.getLocReg();
switch (Reg) {
default:
break;
Expand Down Expand Up @@ -3101,9 +3101,9 @@ M68kTargetLowering::EmitLoweredSelect(MachineInstr &MI,
// destination registers, and the registers that went into the PHI.

for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd; ++MIIt) {
unsigned DestReg = MIIt->getOperand(0).getReg();
unsigned Op1Reg = MIIt->getOperand(1).getReg();
unsigned Op2Reg = MIIt->getOperand(2).getReg();
Register DestReg = MIIt->getOperand(0).getReg();
Register Op1Reg = MIIt->getOperand(1).getReg();
Register Op2Reg = MIIt->getOperand(2).getReg();

// If this CMOV we are generating is the opposite condition from
// the jump we generated, then we have to swap the operands for the
Expand Down Expand Up @@ -3211,13 +3211,13 @@ SDValue M68kTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
auto &MRI = MF.getRegInfo();
auto SPTy = getPointerTy(DAG.getDataLayout());
auto *ARClass = getRegClassFor(SPTy);
unsigned Vreg = MRI.createVirtualRegister(ARClass);
Register Vreg = MRI.createVirtualRegister(ARClass);
Chain = DAG.getCopyToReg(Chain, DL, Vreg, Size);
Result = DAG.getNode(M68kISD::SEG_ALLOCA, DL, SPTy, Chain,
DAG.getRegister(Vreg, SPTy));
} else {
auto &TLI = DAG.getTargetLoweringInfo();
unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
Register SPReg = TLI.getStackPointerRegisterToSaveRestore();
assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
" not tell us which reg is the stack pointer!");

Expand Down
12 changes: 6 additions & 6 deletions llvm/lib/Target/M68k/M68kInstrInfo.cpp
View file
Expand Up @@ -348,8 +348,8 @@ void M68kInstrInfo::AddZExt(MachineBasicBlock &MBB,
bool M68kInstrInfo::ExpandMOVX_RR(MachineInstrBuilder &MIB, MVT MVTDst,
MVT MVTSrc) const {
unsigned Move = MVTDst == MVT::i16 ? M68k::MOV16rr : M68k::MOV32rr;
unsigned Dst = MIB->getOperand(0).getReg();
unsigned Src = MIB->getOperand(1).getReg();
Register Dst = MIB->getOperand(0).getReg();
Register Src = MIB->getOperand(1).getReg();

assert(Dst != Src && "You cannot use the same Regs with MOVX_RR");

Expand Down Expand Up @@ -394,8 +394,8 @@ bool M68kInstrInfo::ExpandMOVSZX_RR(MachineInstrBuilder &MIB, bool IsSigned,
else // i32
Move = M68k::MOV32rr;

unsigned Dst = MIB->getOperand(0).getReg();
unsigned Src = MIB->getOperand(1).getReg();
Register Dst = MIB->getOperand(0).getReg();
Register Src = MIB->getOperand(1).getReg();

assert(Dst != Src && "You cannot use the same Regs with MOVSX_RR");

Expand Down Expand Up @@ -437,7 +437,7 @@ bool M68kInstrInfo::ExpandMOVSZX_RM(MachineInstrBuilder &MIB, bool IsSigned,
MVT MVTSrc) const {
LLVM_DEBUG(dbgs() << "Expand " << *MIB.getInstr() << " to LOAD and ");

unsigned Dst = MIB->getOperand(0).getReg();
Register Dst = MIB->getOperand(0).getReg();

// We need the subreg of Dst to make instruction verifier happy because the
// real machine instruction consumes and produces values of the same size and
Expand Down Expand Up @@ -559,7 +559,7 @@ bool M68kInstrInfo::ExpandMOVEM(MachineInstrBuilder &MIB,
static bool Expand2AddrUndef(MachineInstrBuilder &MIB,
const MCInstrDesc &Desc) {
assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
unsigned Reg = MIB->getOperand(0).getReg();
Register Reg = MIB->getOperand(0).getReg();
MIB->setDesc(Desc);

// MachineInstr::addOperand() will insert explicit operands before any
Expand Down

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