[RISCV] Add missing REQUIRES asserts to test (NFC)

llvm · Dec 20, 2023 · bbe6c81 · bbe6c81
1 parent 2176af7
commit bbe6c81
Showing 1 changed file with 1 addition and 0 deletions.
diff --git a/llvm/test/CodeGen/RISCV/sifive7-enable-intervals.mir b/llvm/test/CodeGen/RISCV/sifive7-enable-intervals.mir
@@ -1,6 +1,7 @@
 # RUN: llc -mtriple=riscv64 -mcpu=sifive-x280 -run-pass=machine-scheduler      \
 # RUN:  -debug-only=machine-scheduler -misched-dump-schedule-trace             \
 # RUN:  -misched-topdown -o - %s 2>&1 | FileCheck %s
+# REQUIRES: asserts
 
 # The purpose of this test is to show that the VADD instructions are issued so
 # that the SiFive7VA is saturated.