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[PowerPC] Fix the assert of ISD::SIGN_EXTEND_INREG when type is v2i16…
… and v2i8 For ISD::SIGN_EXTEND_INREG operation of v2i16 and v2i8 types will cause assert because they are registered as custom operation. So that the type legalization phase will enter the custom hook, which do not handle ISD::SIGN_EXTEND_INREG operation and fall throw into unreachable assert. Patch By: wuzish (Zixuan Wu) Differential Revision: https://reviews.llvm.org/D52449 llvm-svn: 344109
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QingShan Zhang
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Oct 10, 2018
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llvm/test/CodeGen/PowerPC/2018-09-19-sextinreg-vector-crash.ll
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; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-unknown -mcpu=pwr8 | FileCheck %s | ||
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; Ensure this does not crash | ||
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define <2 x i8> @test1(<2 x i8> %a) { | ||
%1 = shl nuw <2 x i8> %a, <i8 7, i8 7> | ||
%2 = ashr exact <2 x i8> %1, <i8 7, i8 7> | ||
ret <2 x i8> %2 | ||
} | ||
; CHECK-LABEL: @test1 | ||
; CHECK: vspltisb [[REG1:[0-9]+]], 7 | ||
; CHECK: vslb [[REG2:[0-9]+]], 2, [[REG1]] | ||
; CHECK: vsrab [[REG3:[0-9]+]], [[REG2]], [[REG1]] | ||
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define <2 x i16> @test2(<2 x i16> %a) { | ||
%1 = shl nuw <2 x i16> %a, <i16 15, i16 15> | ||
%2 = ashr exact <2 x i16> %1, <i16 15, i16 15> | ||
ret <2 x i16> %2 | ||
} | ||
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; CHECK-LABEL: @test2 | ||
; CHECK: vspltish [[REG1:[0-9]+]], 15 | ||
; CHECK: vslh [[REG2:[0-9]+]], 2, [[REG1]] | ||
; CHECK: vsrah [[REG3:[0-9]+]], [[REG2]], [[REG1]] |