AMDGPU: Add testcase from issue 58639

This was fixed in bf789b1
llvm · Nov 1, 2022 · bcedeef · bcedeef
1 parent 71e4e35
commit bcedeef
Showing 1 changed file with 69 additions and 0 deletions.
diff --git a/llvm/test/CodeGen/AMDGPU/attributor-loop-issue-58639.ll b/llvm/test/CodeGen/AMDGPU/attributor-loop-issue-58639.ll
@@ -0,0 +1,69 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --check-globals
+; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -amdgpu-attributor %s | FileCheck %s
+
+%0 = type { double()*, %0* }
+
+define internal fastcc i1 @widget(%0* %arg) {
+; CHECK-LABEL: define {{[^@]+}}@widget
+; CHECK-SAME: (%0* [[ARG:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT:  bb:
+; CHECK-NEXT:    [[TMP:%.*]] = getelementptr inbounds [[TMP0:%.*]], %0* [[ARG]], i64 0, i32 1
+; CHECK-NEXT:    [[TMP1:%.*]] = load %0*, %0** [[TMP]], align 8
+; CHECK-NEXT:    [[TMP2:%.*]] = call fastcc double @baz(%0* [[TMP1]])
+; CHECK-NEXT:    ret i1 false
+;
+bb:
+  %tmp = getelementptr inbounds %0, %0* %arg, i64 0, i32 1
+  %tmp1 = load %0*, %0** %tmp, align 8
+  %tmp2 = call fastcc double @baz(%0* %tmp1)
+  ret i1 false
+}
+
+define internal fastcc double @baz(%0* %arg) {
+; CHECK-LABEL: define {{[^@]+}}@baz
+; CHECK-SAME: (%0* [[ARG:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:  bb:
+; CHECK-NEXT:    [[TMP:%.*]] = getelementptr inbounds [[TMP0:%.*]], %0* [[ARG]], i64 0, i32 0
+; CHECK-NEXT:    [[TMP1:%.*]] = load double ()*, double ()** [[TMP]], align 8
+; CHECK-NEXT:    [[TMP2:%.*]] = tail call double [[TMP1]]()
+; CHECK-NEXT:    br label [[BB3:%.*]]
+; CHECK:       bb3:
+; CHECK-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[TMP0]], %0* [[ARG]], i64 0, i32 1
+; CHECK-NEXT:    br label [[BB5:%.*]]
+; CHECK:       bb5:
+; CHECK-NEXT:    [[TMP6:%.*]] = load %0*, %0** [[TMP4]], align 8
+; CHECK-NEXT:    [[TMP7:%.*]] = call fastcc i1 @widget(%0* [[TMP6]])
+; CHECK-NEXT:    br label [[BB5]]
+;
+bb:
+  %tmp = getelementptr inbounds %0, %0* %arg, i64 0, i32 0
+  %tmp1 = load double ()*, double ()** %tmp, align 8
+  %tmp2 = tail call double %tmp1()
+  br label %bb3
+
+bb3:                                              ; preds = %bb
+  %tmp4 = getelementptr inbounds %0, %0* %arg, i64 0, i32 1
+  br label %bb5
+
+bb5:                                              ; preds = %bb5, %bb3
+  %tmp6 = load %0*, %0** %tmp4, align 8
+  %tmp7 = call fastcc i1 @widget(%0* %tmp6)
+  br label %bb5
+}
+
+define amdgpu_kernel void @entry() {
+; CHECK-LABEL: define {{[^@]+}}@entry
+; CHECK-SAME: () #[[ATTR0]] {
+; CHECK-NEXT:    [[ALLOCA:%.*]] = alloca [[TMP0:%.*]], align 8, addrspace(5)
+; CHECK-NEXT:    [[CAST:%.*]] = addrspacecast [[TMP0]] addrspace(5)* [[ALLOCA]] to %0*
+; CHECK-NEXT:    [[ARST:%.*]] = call double @baz(%0* [[CAST]])
+; CHECK-NEXT:    ret void
+;
+  %alloca = alloca %0, align 8, addrspace(5)
+  %cast = addrspacecast %0 addrspace(5)* %alloca to %0*
+  %arst = call double @baz(%0* %cast)
+  ret void
+}
+;.
+; CHECK: attributes #[[ATTR0]] = { "uniform-work-group-size"="false" }
+;.