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[RISCV] Add (shl (zext GPR:), uimm5:) pattern for -riscv-experimental…
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…-rv64-legal-i32.
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@topperc
topperc committed Nov 11, 2023
1 parent d235cb0 commit bf09636
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Showing 2 changed files with 15 additions and 20 deletions.
5 changes: 5 additions & 0 deletions llvm/lib/Target/RISCV/RISCVInstrInfo.td
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Original file line number Diff line number Diff line change
Expand Up @@ -2050,6 +2050,11 @@ def : Pat<(i32 (and GPR:$rs, TrailingOnesMask:$mask)),

let Predicates = [IsRV64, NotHasStdExtZba] in {
def : Pat<(zext GPR:$src), (SRLI (SLLI GPR:$src, 32), 32)>;

// If we're shifting a 32-bit zero extended value left by 0-31 bits, use 2
// shifts instead of 3. This can occur when unsigned is used to index an array.
def : Pat<(shl (zext GPR:$rs), uimm5:$shamt),
(SRLI (SLLI GPR:$rs, 32), (ImmSubFrom32 uimm5:$shamt))>;
}

//===----------------------------------------------------------------------===//
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30 changes: 10 additions & 20 deletions llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zba.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -50,8 +50,7 @@ define i128 @slliuw_3(i32 signext %0, ptr %1) {
; RV64I: # %bb.0:
; RV64I-NEXT: addi a0, a0, 1
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: slli a0, a0, 4
; RV64I-NEXT: srli a0, a0, 28
; RV64I-NEXT: add a1, a1, a0
; RV64I-NEXT: ld a0, 0(a1)
; RV64I-NEXT: ld a1, 8(a1)
Expand Down Expand Up @@ -1514,8 +1513,7 @@ define signext i32 @srliw_1_sh2add(ptr %0, i32 signext %1) {
; RV64I: # %bb.0:
; RV64I-NEXT: srliw a1, a1, 1
; RV64I-NEXT: slli a1, a1, 32
; RV64I-NEXT: srli a1, a1, 32
; RV64I-NEXT: slli a1, a1, 2
; RV64I-NEXT: srli a1, a1, 30
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: lw a0, 0(a0)
; RV64I-NEXT: ret
Expand All @@ -1539,8 +1537,7 @@ define i64 @srliw_1_sh3add(ptr %0, i32 signext %1) {
; RV64I: # %bb.0:
; RV64I-NEXT: srliw a1, a1, 1
; RV64I-NEXT: slli a1, a1, 32
; RV64I-NEXT: srli a1, a1, 32
; RV64I-NEXT: slli a1, a1, 3
; RV64I-NEXT: srli a1, a1, 29
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ld a0, 0(a0)
; RV64I-NEXT: ret
Expand All @@ -1564,8 +1561,7 @@ define i64 @srliw_2_sh3add(ptr %0, i32 signext %1) {
; RV64I: # %bb.0:
; RV64I-NEXT: srliw a1, a1, 2
; RV64I-NEXT: slli a1, a1, 32
; RV64I-NEXT: srli a1, a1, 32
; RV64I-NEXT: slli a1, a1, 3
; RV64I-NEXT: srli a1, a1, 29
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ld a0, 0(a0)
; RV64I-NEXT: ret
Expand All @@ -1589,8 +1585,7 @@ define signext i16 @srliw_2_sh1add(ptr %0, i32 signext %1) {
; RV64I: # %bb.0:
; RV64I-NEXT: srliw a1, a1, 2
; RV64I-NEXT: slli a1, a1, 32
; RV64I-NEXT: srli a1, a1, 32
; RV64I-NEXT: slli a1, a1, 1
; RV64I-NEXT: srli a1, a1, 31
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: lh a0, 0(a0)
; RV64I-NEXT: ret
Expand All @@ -1615,8 +1610,7 @@ define signext i32 @srliw_3_sh2add(ptr %0, i32 signext %1) {
; RV64I: # %bb.0:
; RV64I-NEXT: srliw a1, a1, 3
; RV64I-NEXT: slli a1, a1, 32
; RV64I-NEXT: srli a1, a1, 32
; RV64I-NEXT: slli a1, a1, 2
; RV64I-NEXT: srli a1, a1, 30
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: lw a0, 0(a0)
; RV64I-NEXT: ret
Expand All @@ -1640,8 +1634,7 @@ define i64 @srliw_4_sh3add(ptr %0, i32 signext %1) {
; RV64I: # %bb.0:
; RV64I-NEXT: srliw a1, a1, 4
; RV64I-NEXT: slli a1, a1, 32
; RV64I-NEXT: srli a1, a1, 32
; RV64I-NEXT: slli a1, a1, 3
; RV64I-NEXT: srli a1, a1, 29
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ld a0, 0(a0)
; RV64I-NEXT: ret
Expand Down Expand Up @@ -1770,8 +1763,7 @@ define signext i16 @shl_2_sh1add(ptr %0, i32 signext %1) {
; RV64I: # %bb.0:
; RV64I-NEXT: slli a1, a1, 2
; RV64I-NEXT: slli a1, a1, 32
; RV64I-NEXT: srli a1, a1, 32
; RV64I-NEXT: slli a1, a1, 1
; RV64I-NEXT: srli a1, a1, 31
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: lh a0, 0(a0)
; RV64I-NEXT: ret
Expand All @@ -1795,8 +1787,7 @@ define signext i32 @shl_16_sh2add(ptr %0, i32 signext %1) {
; RV64I: # %bb.0:
; RV64I-NEXT: slli a1, a1, 16
; RV64I-NEXT: slli a1, a1, 32
; RV64I-NEXT: srli a1, a1, 32
; RV64I-NEXT: slli a1, a1, 2
; RV64I-NEXT: srli a1, a1, 30
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: lw a0, 0(a0)
; RV64I-NEXT: ret
Expand All @@ -1820,8 +1811,7 @@ define i64 @shl_31_sh3add(ptr %0, i32 signext %1) {
; RV64I: # %bb.0:
; RV64I-NEXT: slli a1, a1, 31
; RV64I-NEXT: slli a1, a1, 32
; RV64I-NEXT: srli a1, a1, 32
; RV64I-NEXT: slli a1, a1, 3
; RV64I-NEXT: srli a1, a1, 29
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ld a0, 0(a0)
; RV64I-NEXT: ret
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