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[AArch64][SME] SelectSMETileSlice should also match to 'reg+0' when s…
…lice is ADD with non-constant RHS. It would decompose an address into a `reg + 0` when the slice was not an ADD, but when the RHS of the ADD was not a constant, it would simply not match. This patch fixes that, by always resolving to a `reg + 0` slice.
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35 changes: 35 additions & 0 deletions
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llvm/test/CodeGen/AArch64/sme2-intrinsics-select-sme-tileslice.ll
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 | ||
; RUN: llc < %s | FileCheck %s | ||
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target triple = "aarch64" | ||
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define <vscale x 2 x i64> @test_tileslice_no_add(i32 %idx) #0 { | ||
; CHECK-LABEL: test_tileslice_no_add: | ||
; CHECK: // %bb.0: // %entry | ||
; CHECK-NEXT: mov w8, w0 | ||
; CHECK-NEXT: mov { z0.d, z1.d }, za.d[w8, 0, vgx2] | ||
; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1 | ||
; CHECK-NEXT: ret | ||
entry: | ||
%read = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sme.read.vg1x2.nxv2i64(i32 %idx) | ||
%read.ext = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %read, 0 | ||
ret <vscale x 2 x i64> %read.ext | ||
} | ||
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define <vscale x 2 x i64> @test_tileslice_add_nonconstant(i32 %idx1, i32 %idx2) #0 { | ||
; CHECK-LABEL: test_tileslice_add_nonconstant: | ||
; CHECK: // %bb.0: // %entry | ||
; CHECK-NEXT: add w8, w0, w1 | ||
; CHECK-NEXT: mov { z0.d, z1.d }, za.d[w8, 0, vgx2] | ||
; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1 | ||
; CHECK-NEXT: ret | ||
entry: | ||
%add = add i32 %idx1, %idx2 | ||
%read = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sme.read.vg1x2.nxv2i64(i32 %add) | ||
%read.ext = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %read, 0 | ||
ret <vscale x 2 x i64> %read.ext | ||
} | ||
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declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sme.read.vg1x2.nxv2i64(i32) | ||
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attributes #0 = { nounwind "target-features"="+sme2" } |